shiftreg.tan.summary

来自「verilog实现shiftreg」· SUMMARY 代码 · 共 42 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.211 ns
From           : Di
To             : Q[3]~reg0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 5.713 ns
From           : Q[1]~reg0
To             : Q[1]

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.649 ns
From           : Di
To             : Q[3]~reg0

Type           : Worst-case minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 4.905 ns
From           : Q[2]~reg0
To             : Q[2]

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 290.02 MHz ( period = 3.448 ns )
From           : Q[3]~reg0
To             : Q[2]~reg0

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