shiftreg_5.vhd

来自「verilog实现shiftreg」· VHDL 代码 · 共 33 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY altera;
USE altera.maxplus2.ALL;

ENTITY shiftreg IS
	PORT(Di,clk		 : IN	STD_LOGIC;
		 Q3,Q2,Q1,Q0 : OUT	STD_LOGIC);
END shiftreg;

ARCHITECTURE a OF shiftreg IS
SIGNAL temp : STD_LOGIC_VECTOR(3 downto 1);

BEGIN

d3: dff 
	PORT MAP (d => Di, clk => clk, clrn => '1', prn => '1',
	          q => temp(3));
d2d1:
FOR I IN 2 downto 1 GENERATE
d2: dff 
	PORT MAP (d => temp(I+1), clk => clk, clrn => '1', 
	          prn => '1',q => temp(I));
END GENERATE;
d0: dff 
	PORT MAP (d => temp(1), clk => clk, clrn => '1', 
	          prn => '1', q => Q0);	
Q3<=temp(3); Q2<=temp(2); Q1<=temp(1);
END a;