shiftreg_3.v

来自「verilog实现shiftreg」· Verilog 代码 · 共 16 行

module shiftreg ( Di,clk,Q);
input Di,clk;
output [3:0]Q;
reg [3:0]Q;
integer i;

	always @(posedge clk)
	begin 
		Q(3) <= Di;
		for (i = 3; i > 0; i = i - 1)
     		Q(i-1) <= Q(i);
	end
endmodule