shiftreg_4.vhd

来自「verilog实现shiftreg」· VHDL 代码 · 共 29 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY altera;
USE altera.maxplus2.ALL;
ENTITY shiftreg IS
	PORT(Di,clk		 : IN	STD_LOGIC;
		 Q3,Q2,Q1,Q0 : OUT	STD_LOGIC);
END shiftreg;
ARCHITECTURE a OF shiftreg IS
SIGNAL temp : STD_LOGIC_VECTOR(3 downto 1);

BEGIN
d3: dff 
	PORT MAP (d => Di, clk => clk, clrn => '1', prn => '1',
	          q => temp(3));
d2: dff 
	PORT MAP (d => temp(3), clk => clk, clrn => '1', 
	          prn => '1', q => temp(2));
d1: dff 
   	PORT MAP (d => temp(2), clk => clk, clrn => '1', 
              prn => '1', q => temp(1));
d0: dff 
	PORT MAP (d => temp(1), clk => clk, clrn => '1', 
	          prn => '1', q => Q0);	
END a;