freqtest.map.eqn

基于fpga和sopc的用VHDL语言编写的EDA频率测试与FPGA单片机通讯

--DATA[11] is DATA[11]
--operation mode is normal

DATA[11]_lut_out = DIN[3];
DATA[11] = DFFEA(DATA[11]_lut_out, CLOCK3, VCC, , , , );


--DATA[10] is DATA[10]
--operation mode is normal

DATA[10]_lut_out = DIN[2];
DATA[10] = DFFEA(DATA[10]_lut_out, CLOCK3, VCC, , , , );


--DATA[9] is DATA[9]
--operation mode is normal

DATA[9]_lut_out = DIN[1];
DATA[9] = DFFEA(DATA[9]_lut_out, CLOCK3, VCC, , , , );


--DATA[8] is DATA[8]
--operation mode is normal

DATA[8]_lut_out = DIN[0];
DATA[8] = DFFEA(DATA[8]_lut_out, CLOCK3, VCC, , , , );


--DATA[7] is DATA[7]
--operation mode is normal

DATA[7]_lut_out = DIN[3];
DATA[7] = DFFEA(DATA[7]_lut_out, CLOCK2, VCC, , , , );


--DATA[6] is DATA[6]
--operation mode is normal

DATA[6]_lut_out = DIN[2];
DATA[6] = DFFEA(DATA[6]_lut_out, CLOCK2, VCC, , , , );


--DATA[5] is DATA[5]
--operation mode is normal

DATA[5]_lut_out = DIN[1];
DATA[5] = DFFEA(DATA[5]_lut_out, CLOCK2, VCC, , , , );


--DATA[4] is DATA[4]
--operation mode is normal

DATA[4]_lut_out = DIN[0];
DATA[4] = DFFEA(DATA[4]_lut_out, CLOCK2, VCC, , , , );


--DATA[3] is DATA[3]
--operation mode is normal

DATA[3]_lut_out = DIN[3];
DATA[3] = DFFEA(DATA[3]_lut_out, CLOCK1, VCC, , , , );


--DATA[2] is DATA[2]
--operation mode is normal

DATA[2]_lut_out = DIN[2];
DATA[2] = DFFEA(DATA[2]_lut_out, CLOCK1, VCC, , , , );


--DATA[1] is DATA[1]
--operation mode is normal

DATA[1]_lut_out = DIN[1];
DATA[1] = DFFEA(DATA[1]_lut_out, CLOCK1, VCC, , , , );


--DATA[0] is DATA[0]
--operation mode is normal

DATA[0]_lut_out = DIN[0];
DATA[0] = DFFEA(DATA[0]_lut_out, CLOCK1, VCC, , , , );


--C1_DOUT[23] is REG32B:U2|DOUT[23]
--operation mode is normal

C1_DOUT[23]_lut_out = F6_safe_q[3];
C1_DOUT[23] = DFFEA(C1_DOUT[23]_lut_out, !B1_Div2CLK, VCC, , , , );


--C1_DOUT[27] is REG32B:U2|DOUT[27]
--operation mode is normal

C1_DOUT[27]_lut_out = F7_safe_q[3];
C1_DOUT[27] = DFFEA(C1_DOUT[27]_lut_out, !B1_Div2CLK, VCC, , , , );


--C1_DOUT[19] is REG32B:U2|DOUT[19]
--operation mode is normal

C1_DOUT[19]_lut_out = F5_safe_q[3];
C1_DOUT[19] = DFFEA(C1_DOUT[19]_lut_out, !B1_Div2CLK, VCC, , , , );


--A1L36 is Mux~130
--operation mode is normal

A1L36 = SEL[1] & (SEL[0] # C1_DOUT[27]) # !SEL[1] & !SEL[0] & C1_DOUT[19];


--C1_DOUT[31] is REG32B:U2|DOUT[31]
--operation mode is normal

C1_DOUT[31]_lut_out = F8_safe_q[3];
C1_DOUT[31] = DFFEA(C1_DOUT[31]_lut_out, !B1_Div2CLK, VCC, , , , );


--A1L46 is Mux~131
--operation mode is normal

A1L46 = A1L36 & (C1_DOUT[31] # !SEL[0]) # !A1L36 & C1_DOUT[23] & SEL[0];


--C1_DOUT[11] is REG32B:U2|DOUT[11]
--operation mode is normal

C1_DOUT[11]_lut_out = F3_safe_q[3];
C1_DOUT[11] = DFFEA(C1_DOUT[11]_lut_out, !B1_Div2CLK, VCC, , , , );


--C1_DOUT[7] is REG32B:U2|DOUT[7]
--operation mode is normal

C1_DOUT[7]_lut_out = F2_safe_q[3];
C1_DOUT[7] = DFFEA(C1_DOUT[7]_lut_out, !B1_Div2CLK, VCC, , , , );


--C1_DOUT[3] is REG32B:U2|DOUT[3]
--operation mode is normal

C1_DOUT[3]_lut_out = F1_safe_q[3];
C1_DOUT[3] = DFFEA(C1_DOUT[3]_lut_out, !B1_Div2CLK, VCC, , , , );


--A1L16 is Mux~128
--operation mode is normal

A1L16 = SEL[0] & (SEL[1] # C1_DOUT[7]) # !SEL[0] & !SEL[1] & C1_DOUT[3];


--C1_DOUT[15] is REG32B:U2|DOUT[15]
--operation mode is normal

C1_DOUT[15]_lut_out = F4_safe_q[3];
C1_DOUT[15] = DFFEA(C1_DOUT[15]_lut_out, !B1_Div2CLK, VCC, , , , );


--A1L26 is Mux~129
--operation mode is normal

A1L26 = A1L16 & (C1_DOUT[15] # !SEL[1]) # !A1L16 & C1_DOUT[11] & SEL[1];


--A1L05 is DLOW[3]$latch~66
--operation mode is normal

A1L05 = A1L46 & (A1L26 # SEL[2]) # !A1L46 & A1L26 & !SEL[2];


--A1L25 is DLOW[3]$latch~70
--operation mode is normal

A1L25 = LCELL(A1L25 & (SEL[3] # A1L05) # !A1L25 & !SEL[3] & A1L05);


--C1_DOUT[22] is REG32B:U2|DOUT[22]
--operation mode is normal

C1_DOUT[22]_lut_out = F6_safe_q[2];
C1_DOUT[22] = DFFEA(C1_DOUT[22]_lut_out, !B1_Div2CLK, VCC, , , , );


--C1_DOUT[26] is REG32B:U2|DOUT[26]
--operation mode is normal

C1_DOUT[26]_lut_out = F7_safe_q[2];
C1_DOUT[26] = DFFEA(C1_DOUT[26]_lut_out, !B1_Div2CLK, VCC, , , , );


--C1_DOUT[18] is REG32B:U2|DOUT[18]
--operation mode is normal

C1_DOUT[18]_lut_out = F5_safe_q[2];
C1_DOUT[18] = DFFEA(C1_DOUT[18]_lut_out, !B1_Div2CLK, VCC, , , , );


--A1L76 is Mux~134
--operation mode is normal

A1L76 = SEL[1] & (SEL[0] # C1_DOUT[26]) # !SEL[1] & !SEL[0] & C1_DOUT[18];


--C1_DOUT[30] is REG32B:U2|DOUT[30]
--operation mode is normal

C1_DOUT[30]_lut_out = F8_safe_q[2];
C1_DOUT[30] = DFFEA(C1_DOUT[30]_lut_out, !B1_Div2CLK, VCC, , , , );


--A1L86 is Mux~135
--operation mode is normal

A1L86 = A1L76 & (C1_DOUT[30] # !SEL[0]) # !A1L76 & C1_DOUT[22] & SEL[0];


--C1_DOUT[10] is REG32B:U2|DOUT[10]
--operation mode is normal

C1_DOUT[10]_lut_out = F3_safe_q[2];
C1_DOUT[10] = DFFEA(C1_DOUT[10]_lut_out, !B1_Div2CLK, VCC, , , , );


--C1_DOUT[6] is REG32B:U2|DOUT[6]
--operation mode is normal

C1_DOUT[6]_lut_out = F2_safe_q[2];
C1_DOUT[6] = DFFEA(C1_DOUT[6]_lut_out, !B1_Div2CLK, VCC, , , , );


--C1_DOUT[2] is REG32B:U2|DOUT[2]
--operation mode is normal

C1_DOUT[2]_lut_out = F1_safe_q[2];
C1_DOUT[2] = DFFEA(C1_DOUT[2]_lut_out, !B1_Div2CLK, VCC, , , , );


--A1L56 is Mux~132
--operation mode is normal

A1L56 = SEL[0] & (SEL[1] # C1_DOUT[6]) # !SEL[0] & !SEL[1] & C1_DOUT[2];


--C1_DOUT[14] is REG32B:U2|DOUT[14]
--operation mode is normal

C1_DOUT[14]_lut_out = F4_safe_q[2];
C1_DOUT[14] = DFFEA(C1_DOUT[14]_lut_out, !B1_Div2CLK, VCC, , , , );


--A1L66 is Mux~133
--operation mode is normal

A1L66 = A1L56 & (C1_DOUT[14] # !SEL[1]) # !A1L56 & C1_DOUT[10] & SEL[1];


--A1L64 is DLOW[2]$latch~64
--operation mode is normal

A1L64 = A1L86 & (A1L66 # SEL[2]) # !A1L86 & A1L66 & !SEL[2];


--A1L84 is DLOW[2]$latch~66
--operation mode is normal

A1L84 = LCELL(A1L84 & (SEL[3] # A1L64) # !A1L84 & !SEL[3] & A1L64);


--C1_DOUT[21] is REG32B:U2|DOUT[21]
--operation mode is normal

C1_DOUT[21]_lut_out = F6_safe_q[1];
C1_DOUT[21] = DFFEA(C1_DOUT[21]_lut_out, !B1_Div2CLK, VCC, , , , );


--C1_DOUT[25] is REG32B:U2|DOUT[25]
--operation mode is normal

C1_DOUT[25]_lut_out = F7_safe_q[1];
C1_DOUT[25] = DFFEA(C1_DOUT[25]_lut_out, !B1_Div2CLK, VCC, , , , );


--C1_DOUT[17] is REG32B:U2|DOUT[17]
--operation mode is normal

C1_DOUT[17]_lut_out = F5_safe_q[1];
C1_DOUT[17] = DFFEA(C1_DOUT[17]_lut_out, !B1_Div2CLK, VCC, , , , );


--A1L17 is Mux~138
--operation mode is normal

A1L17 = SEL[1] & (SEL[0] # C1_DOUT[25]) # !SEL[1] & !SEL[0] & C1_DOUT[17];


--C1_DOUT[29] is REG32B:U2|DOUT[29]
--operation mode is normal

C1_DOUT[29]_lut_out = F8_safe_q[1];
C1_DOUT[29] = DFFEA(C1_DOUT[29]_lut_out, !B1_Div2CLK, VCC, , , , );


--A1L27 is Mux~139
--operation mode is normal

A1L27 = A1L17 & (C1_DOUT[29] # !SEL[0]) # !A1L17 & C1_DOUT[21] & SEL[0];


--C1_DOUT[9] is REG32B:U2|DOUT[9]
--operation mode is normal

C1_DOUT[9]_lut_out = F3_safe_q[1];
C1_DOUT[9] = DFFEA(C1_DOUT[9]_lut_out, !B1_Div2CLK, VCC, , , , );


--C1_DOUT[5] is REG32B:U2|DOUT[5]
--operation mode is normal

C1_DOUT[5]_lut_out = F2_safe_q[1];
C1_DOUT[5] = DFFEA(C1_DOUT[5]_lut_out, !B1_Div2CLK, VCC, , , , );


--C1_DOUT[1] is REG32B:U2|DOUT[1]
--operation mode is normal

C1_DOUT[1]_lut_out = F1_safe_q[1];
C1_DOUT[1] = DFFEA(C1_DOUT[1]_lut_out, !B1_Div2CLK, VCC, , , , );


--A1L96 is Mux~136
--operation mode is normal

A1L96 = SEL[0] & (SEL[1] # C1_DOUT[5]) # !SEL[0] & !SEL[1] & C1_DOUT[1];


--C1_DOUT[13] is REG32B:U2|DOUT[13]
--operation mode is normal

C1_DOUT[13]_lut_out = F4_safe_q[1];
C1_DOUT[13] = DFFEA(C1_DOUT[13]_lut_out, !B1_Div2CLK, VCC, , , , );


--A1L07 is Mux~137
--operation mode is normal

A1L07 = A1L96 & (C1_DOUT[13] # !SEL[1]) # !A1L96 & C1_DOUT[9] & SEL[1];


--A1L24 is DLOW[1]$latch~64
--operation mode is normal

A1L24 = A1L27 & (A1L07 # SEL[2]) # !A1L27 & A1L07 & !SEL[2];


--A1L44 is DLOW[1]$latch~66
--operation mode is normal

A1L44 = LCELL(A1L44 & (SEL[3] # A1L24) # !A1L44 & !SEL[3] & A1L24);


--C1_DOUT[20] is REG32B:U2|DOUT[20]
--operation mode is normal

C1_DOUT[20]_lut_out = F6_safe_q[0];
C1_DOUT[20] = DFFEA(C1_DOUT[20]_lut_out, !B1_Div2CLK, VCC, , , , );


--C1_DOUT[24] is REG32B:U2|DOUT[24]
--operation mode is normal

C1_DOUT[24]_lut_out = F7_safe_q[0];
C1_DOUT[24] = DFFEA(C1_DOUT[24]_lut_out, !B1_Div2CLK, VCC, , , , );


--C1_DOUT[16] is REG32B:U2|DOUT[16]
--operation mode is normal

C1_DOUT[16]_lut_out = F5_safe_q[0];
C1_DOUT[16] = DFFEA(C1_DOUT[16]_lut_out, !B1_Div2CLK, VCC, , , , );


--A1L57 is Mux~142
--operation mode is normal

A1L57 = SEL[1] & (SEL[0] # C1_DOUT[24]) # !SEL[1] & !SEL[0] & C1_DOUT[16];


--C1_DOUT[28] is REG32B:U2|DOUT[28]
--operation mode is normal

C1_DOUT[28]_lut_out = F8_safe_q[0];
C1_DOUT[28] = DFFEA(C1_DOUT[28]_lut_out, !B1_Div2CLK, VCC, , , , );


--A1L67 is Mux~143
--operation mode is normal

A1L67 = A1L57 & (C1_DOUT[28] # !SEL[0]) # !A1L57 & C1_DOUT[20] & SEL[0];


--C1_DOUT[8] is REG32B:U2|DOUT[8]
--operation mode is normal

C1_DOUT[8]_lut_out = F3_safe_q[0];
C1_DOUT[8] = DFFEA(C1_DOUT[8]_lut_out, !B1_Div2CLK, VCC, , , , );


--C1_DOUT[4] is REG32B:U2|DOUT[4]
--operation mode is normal

C1_DOUT[4]_lut_out = F2_safe_q[0];
C1_DOUT[4] = DFFEA(C1_DOUT[4]_lut_out, !B1_Div2CLK, VCC, , , , );


--C1_DOUT[0] is REG32B:U2|DOUT[0]
--operation mode is normal

C1_DOUT[0]_lut_out = F1_safe_q[0];
C1_DOUT[0] = DFFEA(C1_DOUT[0]_lut_out, !B1_Div2CLK, VCC, , , , );


--A1L37 is Mux~140
--operation mode is normal

A1L37 = SEL[0] & (SEL[1] # C1_DOUT[4]) # !SEL[0] & !SEL[1] & C1_DOUT[0];


--C1_DOUT[12] is REG32B:U2|DOUT[12]
--operation mode is normal

C1_DOUT[12]_lut_out = F4_safe_q[0];
C1_DOUT[12] = DFFEA(C1_DOUT[12]_lut_out, !B1_Div2CLK, VCC, , , , );


--A1L47 is Mux~141
--operation mode is normal

A1L47 = A1L37 & (C1_DOUT[12] # !SEL[1]) # !A1L37 & C1_DOUT[8] & SEL[1];


--A1L83 is DLOW[0]$latch~64
--operation mode is normal

A1L83 = A1L67 & (A1L47 # SEL[2]) # !A1L67 & A1L47 & !SEL[2];


--A1L04 is DLOW[0]$latch~66
--operation mode is normal

A1L04 = LCELL(A1L04 & (SEL[3] # A1L83) # !A1L04 & !SEL[3] & A1L83);


--CLOCK3 is CLOCK3
--operation mode is normal

CLOCK3 = A1L85 & P37;


--CLOCK2 is CLOCK2
--operation mode is normal

CLOCK2 = P37 & A1L65;


--CLOCK1 is CLOCK1
--operation mode is normal

CLOCK1 = P37 & A1L45;


--F6_safe_q[3] is CNT10:U8|lpm_counter:CQI_rtl_2|cntr_ed8:auto_generated|safe_q[3]
--operation mode is normal

F6_safe_q[3]_carry_eqn = F6L6;
F6_safe_q[3]_lut_out = F6_safe_q[3] $ F6_safe_q[3]_carry_eqn;
F6_safe_q[3]_reg_input = !D6L1 & F6_safe_q[3]_lut_out;
F6_safe_q[3] = DFFEA(F6_safe_q[3]_reg_input, D5L2, !B1_CLR_CNT, , B1_Div2CLK, , );


--B1_Div2CLK is TESTCTL:U1|Div2CLK
--operation mode is normal

B1_Div2CLK_lut_out = !B1_Div2CLK;
B1_Div2CLK = DFFEA(B1_Div2CLK_lut_out, CLK, VCC, , , , );


--F7_safe_q[3] is CNT10:U9|lpm_counter:CQI_rtl_1|cntr_ed8:auto_generated|safe_q[3]
--operation mode is normal

F7_safe_q[3]_carry_eqn = F7L6;
F7_safe_q[3]_lut_out = F7_safe_q[3] $ F7_safe_q[3]_carry_eqn;
F7_safe_q[3]_reg_input = !D7L1 & F7_safe_q[3]_lut_out;
F7_safe_q[3] = DFFEA(F7_safe_q[3]_reg_input, D6L2, !B1_CLR_CNT, , B1_Div2CLK, , );


--F5_safe_q[3] is CNT10:U7|lpm_counter:CQI_rtl_3|cntr_ed8:auto_generated|safe_q[3]
--operation mode is normal

F5_safe_q[3]_carry_eqn = F5L6;
F5_safe_q[3]_lut_out = F5_safe_q[3] $ F5_safe_q[3]_carry_eqn;
F5_safe_q[3]_reg_input = !D5L1 & F5_safe_q[3]_lut_out;
F5_safe_q[3] = DFFEA(F5_safe_q[3]_reg_input, D4L2, !B1_CLR_CNT, , B1_Div2CLK, , );


--F8_safe_q[3] is CNT10:U10|lpm_counter:CQI_rtl_0|cntr_ed8:auto_generated|safe_q[3]
--operation mode is normal

F8_safe_q[3]_carry_eqn = F8L6;
F8_safe_q[3]_lut_out = F8_safe_q[3] $ F8_safe_q[3]_carry_eqn;
F8_safe_q[3]_reg_input = !D8L1 & F8_safe_q[3]_lut_out;
F8_safe_q[3] = DFFEA(F8_safe_q[3]_reg_input, D7L2, !B1_CLR_CNT, , B1_Div2CLK, , );


--F3_safe_q[3] is CNT10:U5|lpm_counter:CQI_rtl_5|cntr_ed8:auto_generated|safe_q[3]
--operation mode is normal

F3_safe_q[3]_carry_eqn = F3L6;
F3_safe_q[3]_lut_out = F3_safe_q[3] $ F3_safe_q[3]_carry_eqn;
F3_safe_q[3]_reg_input = !D3L1 & F3_safe_q[3]_lut_out;
F3_safe_q[3] = DFFEA(F3_safe_q[3]_reg_input, D2L2, !B1_CLR_CNT, , B1_Div2CLK, , );


--F2_safe_q[3] is CNT10:U4|lpm_counter:CQI_rtl_6|cntr_ed8:auto_generated|safe_q[3]
--operation mode is normal

F2_safe_q[3]_carry_eqn = F2L6;
F2_safe_q[3]_lut_out = F2_safe_q[3] $ F2_safe_q[3]_carry_eqn;
F2_safe_q[3]_reg_input = !D2L1 & F2_safe_q[3]_lut_out;
F2_safe_q[3] = DFFEA(F2_safe_q[3]_reg_input, D1L2, !B1_CLR_CNT, , B1_Div2CLK, , );


--F1_safe_q[3] is CNT10:U3|lpm_counter:CQI_rtl_7|cntr_ed8:auto_generated|safe_q[3]
--operation mode is normal

F1_safe_q[3]_carry_eqn = F1L6;
F1_safe_q[3]_lut_out = F1_safe_q[3] $ F1_safe_q[3]_carry_eqn;
F1_safe_q[3]_reg_input = !D1L1 & F1_safe_q[3]_lut_out;
F1_safe_q[3] = DFFEA(F1_safe_q[3]_reg_input, FSIN, !B1_CLR_CNT, , B1_Div2CLK, , );


--F4_safe_q[3] is CNT10:U6|lpm_counter:CQI_rtl_4|cntr_ed8:auto_generated|safe_q[3]
--operation mode is normal

F4_safe_q[3]_carry_eqn = F4L6;
F4_safe_q[3]_lut_out = F4_safe_q[3] $ F4_safe_q[3]_carry_eqn;
F4_safe_q[3]_reg_input = !D4L1 & F4_safe_q[3]_lut_out;
F4_safe_q[3] = DFFEA(F4_safe_q[3]_reg_input, D3L2, !B1_CLR_CNT, , B1_Div2CLK, , );


--F6_safe_q[2] is CNT10:U8|lpm_counter:CQI_rtl_2|cntr_ed8:auto_generated|safe_q[2]
--operation mode is arithmetic

F6_safe_q[2]_carry_eqn = F6L4;
F6_safe_q[2]_lut_out = F6_safe_q[2] $ !F6_safe_q[2]_carry_eqn;
F6_safe_q[2]_reg_input = !D6L1 & F6_safe_q[2]_lut_out;
F6_safe_q[2] = DFFEA(F6_safe_q[2]_reg_input, D5L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F6L6 is CNT10:U8|lpm_counter:CQI_rtl_2|cntr_ed8:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

F6L6 = CARRY(F6_safe_q[2] & !F6L4);


--F7_safe_q[2] is CNT10:U9|lpm_counter:CQI_rtl_1|cntr_ed8:auto_generated|safe_q[2]
--operation mode is arithmetic

F7_safe_q[2]_carry_eqn = F7L4;
F7_safe_q[2]_lut_out = F7_safe_q[2] $ !F7_safe_q[2]_carry_eqn;
F7_safe_q[2]_reg_input = !D7L1 & F7_safe_q[2]_lut_out;
F7_safe_q[2] = DFFEA(F7_safe_q[2]_reg_input, D6L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F7L6 is CNT10:U9|lpm_counter:CQI_rtl_1|cntr_ed8:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

F7L6 = CARRY(F7_safe_q[2] & !F7L4);


--F5_safe_q[2] is CNT10:U7|lpm_counter:CQI_rtl_3|cntr_ed8:auto_generated|safe_q[2]
--operation mode is arithmetic

F5_safe_q[2]_carry_eqn = F5L4;
F5_safe_q[2]_lut_out = F5_safe_q[2] $ !F5_safe_q[2]_carry_eqn;
F5_safe_q[2]_reg_input = !D5L1 & F5_safe_q[2]_lut_out;