freqtest.map.eqn

来自「基于fpga和sopc的用VHDL语言编写的EDA频率测试与FPGA单片机通讯」· EQN 代码 · 共 1,166 行 · 第 1/2 页

F5_safe_q[2] = DFFEA(F5_safe_q[2]_reg_input, D4L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F5L6 is CNT10:U7|lpm_counter:CQI_rtl_3|cntr_ed8:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

F5L6 = CARRY(F5_safe_q[2] & !F5L4);


--F8_safe_q[2] is CNT10:U10|lpm_counter:CQI_rtl_0|cntr_ed8:auto_generated|safe_q[2]
--operation mode is arithmetic

F8_safe_q[2]_carry_eqn = F8L4;
F8_safe_q[2]_lut_out = F8_safe_q[2] $ !F8_safe_q[2]_carry_eqn;
F8_safe_q[2]_reg_input = !D8L1 & F8_safe_q[2]_lut_out;
F8_safe_q[2] = DFFEA(F8_safe_q[2]_reg_input, D7L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F8L6 is CNT10:U10|lpm_counter:CQI_rtl_0|cntr_ed8:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

F8L6 = CARRY(F8_safe_q[2] & !F8L4);


--F3_safe_q[2] is CNT10:U5|lpm_counter:CQI_rtl_5|cntr_ed8:auto_generated|safe_q[2]
--operation mode is arithmetic

F3_safe_q[2]_carry_eqn = F3L4;
F3_safe_q[2]_lut_out = F3_safe_q[2] $ !F3_safe_q[2]_carry_eqn;
F3_safe_q[2]_reg_input = !D3L1 & F3_safe_q[2]_lut_out;
F3_safe_q[2] = DFFEA(F3_safe_q[2]_reg_input, D2L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F3L6 is CNT10:U5|lpm_counter:CQI_rtl_5|cntr_ed8:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

F3L6 = CARRY(F3_safe_q[2] & !F3L4);


--F2_safe_q[2] is CNT10:U4|lpm_counter:CQI_rtl_6|cntr_ed8:auto_generated|safe_q[2]
--operation mode is arithmetic

F2_safe_q[2]_carry_eqn = F2L4;
F2_safe_q[2]_lut_out = F2_safe_q[2] $ !F2_safe_q[2]_carry_eqn;
F2_safe_q[2]_reg_input = !D2L1 & F2_safe_q[2]_lut_out;
F2_safe_q[2] = DFFEA(F2_safe_q[2]_reg_input, D1L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F2L6 is CNT10:U4|lpm_counter:CQI_rtl_6|cntr_ed8:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

F2L6 = CARRY(F2_safe_q[2] & !F2L4);


--F1_safe_q[2] is CNT10:U3|lpm_counter:CQI_rtl_7|cntr_ed8:auto_generated|safe_q[2]
--operation mode is arithmetic

F1_safe_q[2]_carry_eqn = F1L4;
F1_safe_q[2]_lut_out = F1_safe_q[2] $ !F1_safe_q[2]_carry_eqn;
F1_safe_q[2]_reg_input = !D1L1 & F1_safe_q[2]_lut_out;
F1_safe_q[2] = DFFEA(F1_safe_q[2]_reg_input, FSIN, !B1_CLR_CNT, , B1_Div2CLK, , );

--F1L6 is CNT10:U3|lpm_counter:CQI_rtl_7|cntr_ed8:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

F1L6 = CARRY(F1_safe_q[2] & !F1L4);


--F4_safe_q[2] is CNT10:U6|lpm_counter:CQI_rtl_4|cntr_ed8:auto_generated|safe_q[2]
--operation mode is arithmetic

F4_safe_q[2]_carry_eqn = F4L4;
F4_safe_q[2]_lut_out = F4_safe_q[2] $ !F4_safe_q[2]_carry_eqn;
F4_safe_q[2]_reg_input = !D4L1 & F4_safe_q[2]_lut_out;
F4_safe_q[2] = DFFEA(F4_safe_q[2]_reg_input, D3L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F4L6 is CNT10:U6|lpm_counter:CQI_rtl_4|cntr_ed8:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

F4L6 = CARRY(F4_safe_q[2] & !F4L4);


--F6_safe_q[1] is CNT10:U8|lpm_counter:CQI_rtl_2|cntr_ed8:auto_generated|safe_q[1]
--operation mode is arithmetic

F6_safe_q[1]_carry_eqn = F6L2;
F6_safe_q[1]_lut_out = F6_safe_q[1] $ F6_safe_q[1]_carry_eqn;
F6_safe_q[1]_reg_input = !D6L1 & F6_safe_q[1]_lut_out;
F6_safe_q[1] = DFFEA(F6_safe_q[1]_reg_input, D5L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F6L4 is CNT10:U8|lpm_counter:CQI_rtl_2|cntr_ed8:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

F6L4 = CARRY(!F6L2 # !F6_safe_q[1]);


--F7_safe_q[1] is CNT10:U9|lpm_counter:CQI_rtl_1|cntr_ed8:auto_generated|safe_q[1]
--operation mode is arithmetic

F7_safe_q[1]_carry_eqn = F7L2;
F7_safe_q[1]_lut_out = F7_safe_q[1] $ F7_safe_q[1]_carry_eqn;
F7_safe_q[1]_reg_input = !D7L1 & F7_safe_q[1]_lut_out;
F7_safe_q[1] = DFFEA(F7_safe_q[1]_reg_input, D6L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F7L4 is CNT10:U9|lpm_counter:CQI_rtl_1|cntr_ed8:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

F7L4 = CARRY(!F7L2 # !F7_safe_q[1]);


--F5_safe_q[1] is CNT10:U7|lpm_counter:CQI_rtl_3|cntr_ed8:auto_generated|safe_q[1]
--operation mode is arithmetic

F5_safe_q[1]_carry_eqn = F5L2;
F5_safe_q[1]_lut_out = F5_safe_q[1] $ F5_safe_q[1]_carry_eqn;
F5_safe_q[1]_reg_input = !D5L1 & F5_safe_q[1]_lut_out;
F5_safe_q[1] = DFFEA(F5_safe_q[1]_reg_input, D4L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F5L4 is CNT10:U7|lpm_counter:CQI_rtl_3|cntr_ed8:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

F5L4 = CARRY(!F5L2 # !F5_safe_q[1]);


--F8_safe_q[1] is CNT10:U10|lpm_counter:CQI_rtl_0|cntr_ed8:auto_generated|safe_q[1]
--operation mode is arithmetic

F8_safe_q[1]_carry_eqn = F8L2;
F8_safe_q[1]_lut_out = F8_safe_q[1] $ F8_safe_q[1]_carry_eqn;
F8_safe_q[1]_reg_input = !D8L1 & F8_safe_q[1]_lut_out;
F8_safe_q[1] = DFFEA(F8_safe_q[1]_reg_input, D7L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F8L4 is CNT10:U10|lpm_counter:CQI_rtl_0|cntr_ed8:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

F8L4 = CARRY(!F8L2 # !F8_safe_q[1]);


--F3_safe_q[1] is CNT10:U5|lpm_counter:CQI_rtl_5|cntr_ed8:auto_generated|safe_q[1]
--operation mode is arithmetic

F3_safe_q[1]_carry_eqn = F3L2;
F3_safe_q[1]_lut_out = F3_safe_q[1] $ F3_safe_q[1]_carry_eqn;
F3_safe_q[1]_reg_input = !D3L1 & F3_safe_q[1]_lut_out;
F3_safe_q[1] = DFFEA(F3_safe_q[1]_reg_input, D2L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F3L4 is CNT10:U5|lpm_counter:CQI_rtl_5|cntr_ed8:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

F3L4 = CARRY(!F3L2 # !F3_safe_q[1]);


--F2_safe_q[1] is CNT10:U4|lpm_counter:CQI_rtl_6|cntr_ed8:auto_generated|safe_q[1]
--operation mode is arithmetic

F2_safe_q[1]_carry_eqn = F2L2;
F2_safe_q[1]_lut_out = F2_safe_q[1] $ F2_safe_q[1]_carry_eqn;
F2_safe_q[1]_reg_input = !D2L1 & F2_safe_q[1]_lut_out;
F2_safe_q[1] = DFFEA(F2_safe_q[1]_reg_input, D1L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F2L4 is CNT10:U4|lpm_counter:CQI_rtl_6|cntr_ed8:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

F2L4 = CARRY(!F2L2 # !F2_safe_q[1]);


--F1_safe_q[1] is CNT10:U3|lpm_counter:CQI_rtl_7|cntr_ed8:auto_generated|safe_q[1]
--operation mode is arithmetic

F1_safe_q[1]_carry_eqn = F1L2;
F1_safe_q[1]_lut_out = F1_safe_q[1] $ F1_safe_q[1]_carry_eqn;
F1_safe_q[1]_reg_input = !D1L1 & F1_safe_q[1]_lut_out;
F1_safe_q[1] = DFFEA(F1_safe_q[1]_reg_input, FSIN, !B1_CLR_CNT, , B1_Div2CLK, , );

--F1L4 is CNT10:U3|lpm_counter:CQI_rtl_7|cntr_ed8:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

F1L4 = CARRY(!F1L2 # !F1_safe_q[1]);


--F4_safe_q[1] is CNT10:U6|lpm_counter:CQI_rtl_4|cntr_ed8:auto_generated|safe_q[1]
--operation mode is arithmetic

F4_safe_q[1]_carry_eqn = F4L2;
F4_safe_q[1]_lut_out = F4_safe_q[1] $ F4_safe_q[1]_carry_eqn;
F4_safe_q[1]_reg_input = !D4L1 & F4_safe_q[1]_lut_out;
F4_safe_q[1] = DFFEA(F4_safe_q[1]_reg_input, D3L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F4L4 is CNT10:U6|lpm_counter:CQI_rtl_4|cntr_ed8:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

F4L4 = CARRY(!F4L2 # !F4_safe_q[1]);


--F6_safe_q[0] is CNT10:U8|lpm_counter:CQI_rtl_2|cntr_ed8:auto_generated|safe_q[0]
--operation mode is arithmetic

F6_safe_q[0]_lut_out = !F6_safe_q[0];
F6_safe_q[0]_reg_input = !D6L1 & F6_safe_q[0]_lut_out;
F6_safe_q[0] = DFFEA(F6_safe_q[0]_reg_input, D5L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F6L2 is CNT10:U8|lpm_counter:CQI_rtl_2|cntr_ed8:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

F6L2 = CARRY(F6_safe_q[0]);


--F7_safe_q[0] is CNT10:U9|lpm_counter:CQI_rtl_1|cntr_ed8:auto_generated|safe_q[0]
--operation mode is arithmetic

F7_safe_q[0]_lut_out = !F7_safe_q[0];
F7_safe_q[0]_reg_input = !D7L1 & F7_safe_q[0]_lut_out;
F7_safe_q[0] = DFFEA(F7_safe_q[0]_reg_input, D6L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F7L2 is CNT10:U9|lpm_counter:CQI_rtl_1|cntr_ed8:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

F7L2 = CARRY(F7_safe_q[0]);


--F5_safe_q[0] is CNT10:U7|lpm_counter:CQI_rtl_3|cntr_ed8:auto_generated|safe_q[0]
--operation mode is arithmetic

F5_safe_q[0]_lut_out = !F5_safe_q[0];
F5_safe_q[0]_reg_input = !D5L1 & F5_safe_q[0]_lut_out;
F5_safe_q[0] = DFFEA(F5_safe_q[0]_reg_input, D4L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F5L2 is CNT10:U7|lpm_counter:CQI_rtl_3|cntr_ed8:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

F5L2 = CARRY(F5_safe_q[0]);


--F8_safe_q[0] is CNT10:U10|lpm_counter:CQI_rtl_0|cntr_ed8:auto_generated|safe_q[0]
--operation mode is arithmetic

F8_safe_q[0]_lut_out = !F8_safe_q[0];
F8_safe_q[0]_reg_input = !D8L1 & F8_safe_q[0]_lut_out;
F8_safe_q[0] = DFFEA(F8_safe_q[0]_reg_input, D7L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F8L2 is CNT10:U10|lpm_counter:CQI_rtl_0|cntr_ed8:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

F8L2 = CARRY(F8_safe_q[0]);


--F3_safe_q[0] is CNT10:U5|lpm_counter:CQI_rtl_5|cntr_ed8:auto_generated|safe_q[0]
--operation mode is arithmetic

F3_safe_q[0]_lut_out = !F3_safe_q[0];
F3_safe_q[0]_reg_input = !D3L1 & F3_safe_q[0]_lut_out;
F3_safe_q[0] = DFFEA(F3_safe_q[0]_reg_input, D2L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F3L2 is CNT10:U5|lpm_counter:CQI_rtl_5|cntr_ed8:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

F3L2 = CARRY(F3_safe_q[0]);


--F2_safe_q[0] is CNT10:U4|lpm_counter:CQI_rtl_6|cntr_ed8:auto_generated|safe_q[0]
--operation mode is arithmetic

F2_safe_q[0]_lut_out = !F2_safe_q[0];
F2_safe_q[0]_reg_input = !D2L1 & F2_safe_q[0]_lut_out;
F2_safe_q[0] = DFFEA(F2_safe_q[0]_reg_input, D1L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F2L2 is CNT10:U4|lpm_counter:CQI_rtl_6|cntr_ed8:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

F2L2 = CARRY(F2_safe_q[0]);


--F1_safe_q[0] is CNT10:U3|lpm_counter:CQI_rtl_7|cntr_ed8:auto_generated|safe_q[0]
--operation mode is arithmetic

F1_safe_q[0]_lut_out = !F1_safe_q[0];
F1_safe_q[0]_reg_input = !D1L1 & F1_safe_q[0]_lut_out;
F1_safe_q[0] = DFFEA(F1_safe_q[0]_reg_input, FSIN, !B1_CLR_CNT, , B1_Div2CLK, , );

--F1L2 is CNT10:U3|lpm_counter:CQI_rtl_7|cntr_ed8:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

F1L2 = CARRY(F1_safe_q[0]);


--F4_safe_q[0] is CNT10:U6|lpm_counter:CQI_rtl_4|cntr_ed8:auto_generated|safe_q[0]
--operation mode is arithmetic

F4_safe_q[0]_lut_out = !F4_safe_q[0];
F4_safe_q[0]_reg_input = !D4L1 & F4_safe_q[0]_lut_out;
F4_safe_q[0] = DFFEA(F4_safe_q[0]_reg_input, D3L2, !B1_CLR_CNT, , B1_Div2CLK, , );

--F4L2 is CNT10:U6|lpm_counter:CQI_rtl_4|cntr_ed8:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

F4L2 = CARRY(F4_safe_q[0]);


--A1L77 is Mux~189
--operation mode is normal

A1L77 = SEL[3] & !SEL[2];


--A1L85 is K3~61
--operation mode is normal

A1L85 = LCELL(A1L77 & (SEL[1] & !SEL[0] # !SEL[1] & A1L85));


--A1L65 is K2~61
--operation mode is normal

A1L65 = LCELL(A1L77 & (SEL[0] & !SEL[1] # !SEL[0] & A1L65));


--A1L06 is Mux~113
--operation mode is normal

A1L06 = !SEL[2] & SEL[3] & (SEL[0] $ SEL[1]);


--A1L45 is K1~46
--operation mode is normal

A1L45 = LCELL(A1L06 & A1L45 # !A1L06 & A1L77 & !SEL[0]);


--D5L2 is CNT10:U7|reduce_nor~12
--operation mode is normal

D5L2 = !F5_safe_q[2] & !F5_safe_q[1] & F5_safe_q[3] & F5_safe_q[0];


--B1_CLR_CNT is TESTCTL:U1|CLR_CNT
--operation mode is normal

B1_CLR_CNT = !B1_Div2CLK & !CLK;


--D6L1 is CNT10:U8|LessThan~14
--operation mode is normal

D6L1 = F6_safe_q[3] & (F6_safe_q[2] # F6_safe_q[1] # F6_safe_q[0]);


--D6L2 is CNT10:U8|reduce_nor~12
--operation mode is normal

D6L2 = !F6_safe_q[2] & !F6_safe_q[1] & F6_safe_q[3] & F6_safe_q[0];


--D7L1 is CNT10:U9|LessThan~14
--operation mode is normal

D7L1 = F7_safe_q[3] & (F7_safe_q[2] # F7_safe_q[1] # F7_safe_q[0]);


--D4L2 is CNT10:U6|reduce_nor~12
--operation mode is normal

D4L2 = !F4_safe_q[2] & !F4_safe_q[1] & F4_safe_q[3] & F4_safe_q[0];


--D5L1 is CNT10:U7|LessThan~14
--operation mode is normal

D5L1 = F5_safe_q[3] & (F5_safe_q[2] # F5_safe_q[1] # F5_safe_q[0]);


--D7L2 is CNT10:U9|reduce_nor~12
--operation mode is normal

D7L2 = !F7_safe_q[2] & !F7_safe_q[1] & F7_safe_q[3] & F7_safe_q[0];


--D8L1 is CNT10:U10|LessThan~14
--operation mode is normal

D8L1 = F8_safe_q[3] & (F8_safe_q[2] # F8_safe_q[1] # F8_safe_q[0]);


--D2L2 is CNT10:U4|reduce_nor~12
--operation mode is normal

D2L2 = !F2_safe_q[2] & !F2_safe_q[1] & F2_safe_q[3] & F2_safe_q[0];


--D3L1 is CNT10:U5|LessThan~14
--operation mode is normal

D3L1 = F3_safe_q[3] & (F3_safe_q[2] # F3_safe_q[1] # F3_safe_q[0]);


--D1L2 is CNT10:U3|reduce_nor~12
--operation mode is normal

D1L2 = !F1_safe_q[2] & !F1_safe_q[1] & F1_safe_q[3] & F1_safe_q[0];


--D2L1 is CNT10:U4|LessThan~14
--operation mode is normal

D2L1 = F2_safe_q[3] & (F2_safe_q[2] # F2_safe_q[1] # F2_safe_q[0]);


--D1L1 is CNT10:U3|LessThan~14
--operation mode is normal

D1L1 = F1_safe_q[3] & (F1_safe_q[2] # F1_safe_q[1] # F1_safe_q[0]);


--D3L2 is CNT10:U5|reduce_nor~12
--operation mode is normal

D3L2 = !F3_safe_q[2] & !F3_safe_q[1] & F3_safe_q[3] & F3_safe_q[0];


--D4L1 is CNT10:U6|LessThan~14
--operation mode is normal

D4L1 = F4_safe_q[3] & (F4_safe_q[2] # F4_safe_q[1] # F4_safe_q[0]);


--SEL[3] is SEL[3]
--operation mode is input

SEL[3] = INPUT();


--SEL[0] is SEL[0]
--operation mode is input

SEL[0] = INPUT();


--SEL[1] is SEL[1]
--operation mode is input

SEL[1] = INPUT();


--SEL[2] is SEL[2]
--operation mode is input

SEL[2] = INPUT();


--DIN[3] is DIN[3]
--operation mode is input

DIN[3] = INPUT();


--P37 is P37
--operation mode is input

P37 = INPUT();


--DIN[2] is DIN[2]
--operation mode is input

DIN[2] = INPUT();


--DIN[1] is DIN[1]
--operation mode is input

DIN[1] = INPUT();


--DIN[0] is DIN[0]
--operation mode is input

DIN[0] = INPUT();


--CLK is CLK
--operation mode is input

CLK = INPUT();


--FSIN is FSIN
--operation mode is input

FSIN = INPUT();


--DLOW[3] is DLOW[3]
--operation mode is output

DLOW[3] = OUTPUT(A1L25);


--DLOW[2] is DLOW[2]
--operation mode is output

DLOW[2] = OUTPUT(A1L84);


--DLOW[1] is DLOW[1]
--operation mode is output

DLOW[1] = OUTPUT(A1L44);


--DLOW[0] is DLOW[0]
--operation mode is output

DLOW[0] = OUTPUT(A1L04);


--DATAOUT[11] is DATAOUT[11]
--operation mode is output

DATAOUT[11] = OUTPUT(DATA[11]);


--DATAOUT[10] is DATAOUT[10]
--operation mode is output

DATAOUT[10] = OUTPUT(DATA[10]);


--DATAOUT[9] is DATAOUT[9]
--operation mode is output

DATAOUT[9] = OUTPUT(DATA[9]);


--DATAOUT[8] is DATAOUT[8]
--operation mode is output

DATAOUT[8] = OUTPUT(DATA[8]);


--DATAOUT[7] is DATAOUT[7]
--operation mode is output

DATAOUT[7] = OUTPUT(DATA[7]);


--DATAOUT[6] is DATAOUT[6]
--operation mode is output

DATAOUT[6] = OUTPUT(DATA[6]);


--DATAOUT[5] is DATAOUT[5]
--operation mode is output

DATAOUT[5] = OUTPUT(DATA[5]);


--DATAOUT[4] is DATAOUT[4]
--operation mode is output

DATAOUT[4] = OUTPUT(DATA[4]);


--DATAOUT[3] is DATAOUT[3]
--operation mode is output

DATAOUT[3] = OUTPUT(DATA[3]);


--DATAOUT[2] is DATAOUT[2]
--operation mode is output

DATAOUT[2] = OUTPUT(DATA[2]);


--DATAOUT[1] is DATAOUT[1]
--operation mode is output

DATAOUT[1] = OUTPUT(DATA[1]);


--DATAOUT[0] is DATAOUT[0]
--operation mode is output

DATAOUT[0] = OUTPUT(DATA[0]);