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VHDL设计的数字时钟

Compiling vhdl file D:/Xilinx/bin/200404015010/wangyicheng.vhd in Library work.
Entity <szz> (Architecture <one>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <szz> (Architecture <one>).
WARNING:Xst:819 - D:/Xilinx/bin/200404015010/wangyicheng.vhd line 424: The following signals are missing in the process sensitivity list:
   pp, h1, h2, m1, m2, s1, s2.
INFO:Xst:1304 - Contents of register <pp> in unit <szz> never changes during circuit operation. The register is replaced by logic.
Entity <szz> analyzed. Unit <szz> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <szz>.
    Related source file is D:/Xilinx/bin/200404015010/wangyicheng.vhd.
WARNING:Xst:737 - Found 4-bit latch for signal <selout>.
WARNING:Xst:737 - Found 8-bit latch for signal <dout>.
    Found 1-bit register for signal <speak>.
    Found 4-bit comparator equal for signal <$n0134> created at line 408.
    Found 4-bit comparator equal for signal <$n0135> created at line 408.
    Found 4-bit comparator equal for signal <$n0136> created at line 408.
    Found 4-bit comparator equal for signal <$n0137> created at line 408.
    Found 32-bit up counter for signal <a>.
    Found 32-bit up counter for signal <b>.
    Found 32-bit up counter for signal <c>.
    Found 1-bit register for signal <clk>.
    Found 1-bit register for signal <clk1>.
    Found 1-bit register for signal <clk2>.
    Found 1-bit register for signal <clk3>.
    Found 32-bit up counter for signal <d>.
    Found 4-bit up counter for signal <hou1>.
    Found 4-bit up counter for signal <hou2>.
    Found 4-bit up counter for signal <min1>.
    Found 4-bit up counter for signal <min2>.
    Found 1-bit register for signal <pp>.
    Found 4-bit up counter for signal <sec1>.
    Found 4-bit up counter for signal <sec2>.
    Found 3-bit up counter for signal <sel>.
    Found 4-bit up counter for signal <seth1>.
    Found 4-bit up counter for signal <seth2>.
    Found 4-bit up counter for signal <setm1>.
    Found 4-bit up counter for signal <setm2>.
    Found 16 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  15 Counter(s).
	inferred   6 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred  16 Multiplexer(s).
Unit <szz> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 14
 32-bit up counter                 : 3
 4-bit up counter                  : 10
 3-bit up counter                  : 1
# Registers                        : 5
 1-bit register                    : 5
# Latches                          : 2
 8-bit latch                       : 1
 4-bit latch                       : 1
# Comparators                      : 4
 4-bit comparator equal            : 4
# Multiplexers                     : 4
 4-bit 2-to-1 multiplexer          : 4

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch pp hinder the constant cleaning in the block szz.
   You should achieve better results by setting this init to 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Completed process "View RTL Schematic".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "View RTL Schematic".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file D:\Xilinx\bin\200404015010/wangyicheng.vhd, automatic determination of correct order of compilation of files in project file szz_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.
Compiling vhdl file D:\Xilinx\bin\200404015010/wangyicheng.vhd in Library work.
ERROR:HDLParsers:164 - D:\Xilinx\bin\200404015010/wangyicheng.vhd Line 590. parse error, unexpected END, expecting SEMICOLON
ERROR:HDLParsers:164 - D:\Xilinx\bin\200404015010/wangyicheng.vhd Line 614. parse error, unexpected PROCESS, expecting IF
--> 

Total memory usage is 48512 kilobytes


ERROR: XST failed
Process "View RTL Schematic" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "View RTL Schematic".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/Xilinx/bin/200404015010/wangyicheng.vhd in Library work.
Entity <szz> (Architecture <one>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <szz> (Architecture <one>).
WARNING:Xst:819 - D:/Xilinx/bin/200404015010/wangyicheng.vhd line 424: The following signals are missing in the process sensitivity list:
   pp, h1, h2, m1, m2, s1, s2.
INFO:Xst:1304 - Contents of register <pp> in unit <szz> never changes during circuit operation. The register is replaced by logic.
Entity <szz> analyzed. Unit <szz> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <szz>.
    Related source file is D:/Xilinx/bin/200404015010/wangyicheng.vhd.
WARNING:Xst:737 - Found 4-bit latch for signal <selout>.
WARNING:Xst:737 - Found 8-bit latch for signal <dout>.
    Found 1-bit register for signal <speak>.
    Found 4-bit comparator equal for signal <$n0136> created at line 408.
    Found 4-bit comparator equal for signal <$n0137> created at line 408.
    Found 4-bit com