scc2.v

一维DCT变换的verilog源码

`timescale 1ns/10ps     
`define bw  12          
//scc42 skew-circular convolution                         
module scc2(//input         
               nrst,clk,
               scc2en,
               scc2en_d,
               di,  
             //output        
               do);          
input  nrst,clk;
input  scc2en,scc2en_d;
input  [`bw-1:0] di;
output [`bw-1:0] do;

reg  [`bw-1:0] sccreg1, sccreg2; //参与运算的两个数
wire [`bw-1:0] sccreg_in=scc2en?di:sccreg2;

wire sccreg1en= scc2en | scc2en_d;
always @(posedge clk or negedge nrst)
 if (~nrst)         sccreg1<=0;
 else if (sccreg1en)sccreg1<=sccreg_in;
 
wire scc2en_n=~scc2en & scc2en_d;
always @(posedge clk or negedge nrst)
 if (~nrst)         sccreg2<=0;
 else if (scc2en_n) sccreg2<=~sccreg1+1;      //补码
 else if (scc2en_d) sccreg2<= sccreg1;
// else               sccreg2<=0;

//==============================================================================================================
// multiplier part      
//0.1913417 multiplier        1/2*cos(3*pi/8)=0.0011_0000_1111_101=0.010-1_0001_0000_-101                    
wire [`bw-1:0] csa4_2= sccreg1;
wire [`bw-1:0] csa4_3= (sccreg1[`bw-1]==1)? {2'b0,~sccreg1[`bw-1:2]}:{2'b11,~sccreg1[`bw-1:2]}; //csa4_3是负的      
wire [`bw-1:0] csa4_4= (sccreg1[`bw-1]==1)? {{6{1'b1}},sccreg1[`bw-1:6]}:{6'b0,sccreg1[`bw-1:6]};     
wire [`bw+1:0] sum019_tmp;
wire [`bw:0]   sum019=sum019_tmp[`bw+1:1];
csa4 csa4( .a1({11'b0,1'b1}), .a2(csa4_2), .a3(csa4_3), .a4(csa4_4), .sum(sum019_tmp));


//0.4619337 multiplier        1/2*cos(pi/8)=0.0111_0110_01=0.100-1_10-10_01
wire [`bw-1:0] csa5_2= sccreg2;
wire [`bw-1:0] csa5_3=(sccreg2[`bw-1]==1)? {4'b0,~sccreg2[`bw-1:4]}:{{4{1'b1}},~sccreg2[`bw-1:4]}; //csa5_3是负的  
wire [`bw-1:0] csa5_4=(sccreg2[`bw-1]==1)? {6'b0,~sccreg2[`bw-1:6]}:{{6{1'b1}},~sccreg2[`bw-1:6]}; //csa5_4是负的
wire [`bw-1:0] csa5_5=(sccreg2[`bw-1]==1)? {{9{1'b1}},sccreg2[`bw-1:9]}:{9'b0,sccreg2[`bw-1:9]};
wire [`bw+2:0] sum046_tmp;
wire [`bw:0]   sum046=sum046_tmp[`bw:0];
csa5 csa5( .a1({10'b0,2'b10}), .a2(csa5_2), .a3(csa5_3), .a4(csa5_4), .a5(csa5_5), .sum(sum046_tmp)); 

wire [`bw:0] do_tmp=sum019+sum046;                      
wire [`bw-1:0] do=do_tmp[`bw:1];				//?? why
                                                
endmodule