dct_1d.map.summary

来自「一维DCT变换的verilog源码」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Fri Jun 22 11:07:19 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : dct_1d
Top-level Entity Name : dct_1d
Family : Cyclone II
Total logic elements : 1560
Total registers : 207
Total pins : 56
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0