📄 dct_1d.map.rpt
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; -- arithmetic mode ; 264 ;
; Total registers ; 207 ;
; I/O pins ; 56 ;
; Maximum fan-out node ; dcten ;
; Maximum fan-out ; 421 ;
; Total fan-out ; 6233 ;
; Average fan-out ; 3.42 ;
+---------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+-------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+-------------------------------+
; |dct_1d ; 1560 (433) ; 207 (15) ; 0 ; 0 ; 0 ; 0 ; 0 ; 56 ; 0 ; |dct_1d ;
; |add:add| ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dct_1d|add:add ;
; |csa4:csa41| ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dct_1d|csa4:csa41 ;
; |csa4:csa42| ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dct_1d|csa4:csa42 ;
; |csa4:csa43| ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dct_1d|csa4:csa43 ;
; |csa4:csa44| ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dct_1d|csa4:csa44 ;
; |csa51:csa55| ; 79 (79) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dct_1d|csa51:csa55 ;
; |csa5:csa51| ; 96 (96) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dct_1d|csa5:csa51 ;
; |csa5:csa52| ; 100 (100) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dct_1d|csa5:csa52 ;
; |scc2:scc2| ; 162 (55) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dct_1d|scc2:scc2 ;
; |csa4:csa4| ; 43 (43) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dct_1d|scc2:scc2|csa4:csa4 ;
; |csa5:csa5| ; 64 (64) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dct_1d|scc2:scc2|csa5:csa5 ;
; |scc4:scc4| ; 418 (136) ; 168 (168) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dct_1d|scc4:scc4 ;
; |csa52:csa53| ; 89 (89) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dct_1d|scc4:scc4|csa52:csa53 ;
; |csa5:csa51| ; 58 (58) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dct_1d|scc4:scc4|csa5:csa51 ;
; |csa5:csa52| ; 64 (64) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dct_1d|scc4:scc4|csa5:csa52 ;
; |csa6:csa6| ; 71 (71) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dct_1d|scc4:scc4|csa6:csa6 ;
; |sub:sub| ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dct_1d|sub:sub ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+-------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 207 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 15 ;
; Number of registers using Asynchronous Clear ; 183 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 183 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |dct_1d|fodd_d[12] ;
; 3:1 ; 12 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |dct_1d|fodd_d[10] ;
; 3:1 ; 12 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |dct_1d|scc2:scc2|sccreg2[5] ;
; 6:1 ; 12 bits ; 48 LEs ; 36 LEs ; 12 LEs ; Yes ; |dct_1d|scc2:scc2|sccreg1[2] ;
; 3:1 ; 15 bits ; 30 LEs ; 30 LEs ; 0 LEs ; No ; |dct_1d|comb~710 ;
; 3:1 ; 12 bits ; 24 LEs ; 12 LEs ; 12 LEs ; No ; |dct_1d|scc4_in[1] ;
; 3:1 ; 68 bits ; 136 LEs ; 136 LEs ; 0 LEs ; No ; |dct_1d|csa44_a2[2] ;
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |dct_1d|ae2[1] ;
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |dct_1d|ae1[1] ;
; 4:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |dct_1d|comb~36 ;
; 9:1 ; 12 bits ; 72 LEs ; 48 LEs ; 24 LEs ; No ; |dct_1d|stmp[5] ;
; 9:1 ; 12 bits ; 72 LEs ; 48 LEs ; 24 LEs ; No ; |dct_1d|scc4:scc4|Add0 ;
; 12:1 ; 12 bits ; 96 LEs ; 60 LEs ; 36 LEs ; No ; |dct_1d|scc4:scc4|Add0 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Fri Jun 22 11:06:54 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dct_1d -c dct_1d
Info: Found 1 design units, including 1 entities, in source file csa51.v
Info: Found entity 1: csa51
Warning (10274): Verilog HDL macro warning at csa5.v(4): overriding existing definition for macro "width", which was defined in "csa51.v", line 4
Info: Found 1 design units, including 1 entities, in source file csa5.v
Info: Found entity 1: csa5
Warning (10274): Verilog HDL macro warning at csa52.v(4): overriding existing definition for macro "width", which was defined in "csa51.v", line 4
Info: Found 1 design units, including 1 entities, in source file csa52.v
Info: Found entity 1: csa52
Info: Found 1 design units, including 1 entities, in source file csa6.v
Info: Found entity 1: csa6
Info: Found 1 design units, including 1 entities, in source file add.v
Info: Found entity 1: add
Warning (10274): Verilog HDL macro warning at csa4.v(3): overriding existing definition for macro "width", which was defined in "csa51.v", line 4
Info: Found 1 design units, including 1 entities, in source file csa4.v
Info: Found entity 1: csa4
Warning (10463): Verilog HDL Declaration warning at dct_1d.v(97): "do" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at dct_1d.v(154): "do" is SystemVerilog-2005 keyword
Info: Found 1 design units, including 1 entities, in source file dct_1d.v
Info: Found entity 1: dct_1d
Warning (10274): Verilog HDL macro warning at scc2.v(3): overriding existing definition for macro "bw", which was defined in "add.v", line 3
Warning (10463): Verilog HDL Declaration warning at scc2.v(10): "do" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at scc2.v(14): "do" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at scc2.v(52): "do" is SystemVerilog-2005 keyword
Info: Found 1 design units, including 1 entities, in source file scc2.v
Info: Found entity 1: scc2
Warning (10274): Verilog HDL macro warning at scc4.v(3): overriding existing definition for macro "bw", which was defined in "add.v", line 3
Warning (10463): Verilog HDL Declaration warning at scc4.v(17): "do" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at scc4.v(28): "do" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at scc4.v(125): "do" is SystemVerilog-2005 keyword
Info: Found 1 design units, including 1 entities, in source file scc4.v
Info: Found entity 1: scc4
Warning (10274): Verilog HDL macro warning at sub.v(3): overriding existing definition for macro "bw", which was defined in "add.v", line 3
Info: Found 1 design units, including 1 entities, in source file sub.v
Info: Found entity 1: sub
Info: Elaborating entity "dct_1d" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at dct_1d.v(105): object "f01en" assigned a value but never read
Info: Elaborating entity "scc4" for hierarchy "scc4:scc4"
Info: Elaborating entity "sub" for hierarchy "scc4:scc4|sub:sub"
Info: Elaborating entity "csa6" for hierarchy "scc4:scc4|csa6:csa6"
Warning (10036): Verilog HDL or VHDL warning at csa6.v(34): object "test0" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at csa6.v(43): object "test1" assigned a value but never read
Info: Elaborating entity "csa5" for hierarchy "scc4:scc4|csa5:csa51"
Warning (10230): Verilog HDL assignment warning at csa5.v(44): truncated value with size 16 to match size of target (15)
Warning (10230): Verilog HDL assignment warning at csa5.v(45): truncated value with size 16 to match size of target (15)
Info: Elaborating entity "csa52" for hierarchy "scc4:scc4|csa52:csa53"
Warning (10230): Verilog HDL assignment warning at csa52.v(44): truncated value with size 17 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at csa52.v(45): truncated value with size 17 to match size of target (16)
Info: Elaborating entity "scc2" for hierarchy "scc2:scc2"
Warning (10230): Verilog HDL assignment warning at scc2.v(27): truncated value with size 32 to match size of target (12)
Info: Elaborating entity "csa4" for hierarchy "scc2:scc2|csa4:csa4"
Info: Elaborating entity "csa51" for hierarchy "csa51:csa55"
Warning (10230): Verilog HDL assignment warning at csa51.v(44): truncated value with size 19 to match size of target (18)
Warning (10230): Verilog HDL assignment warning at csa51.v(45): truncated value with size 19 to match size of target (18)
Info: Elaborating entity "add" for hierarchy "add:add"
Warning: Port "sum" on the entity instantiation of "csa55" is connected to a signal of width 14. The formal width of the signal in the module is 18. Extra bits will be left dangling without any fanout logic.
Warning: Port "sum" on the entity instantiation of "csa52" is connected to a signal of width 14. The formal width of the signal in the module is 15. Extra bits will be left dangling without any fanout logic.
Warning: Port "sum" on the entity instantiation of "csa51" is connected to a signal of width 14. The formal width of the signal in the module is 15. Extra bits will be left dangling without any fanout logic.
Info: Implemented 1772 device resources after synthesis - the final resource count might be different
Info: Implemented 20 input pins
Info: Implemented 36 output pins
Info: Implemented 1716 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 27 warnings
Info: Processing ended: Fri Jun 22 11:07:19 2007
Info: Elapsed time: 00:00:25
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