scc4.v

一维DCT变换的verilog源码

`timescale 1ns/10ps
`define bw  12    
//use 12 flip flop 

module scc4(//input
               nrst,clk,
               dcten,idcten,
               
               scc4en,scc4en_d,
               
               a0en,a1en,a2en,a3en,
               a4en,a5en,a6en,a7en,
               sub1en,sub2en,sub3en,sub4en,
               di,
            //output
               a0,a1,a2,a3,a4,a5,a6,a7,                      
               do);
               
input  nrst,clk;
input  dcten,idcten;
input  scc4en,scc4en_d;    
input  a0en,a1en,a2en,a3en;   
input  a4en,a5en,a6en,a7en;   
input  sub1en,sub2en,sub3en,sub4en;    
    
input  [`bw-1:0] di; 
output [`bw-1:0] a0,a1,a2,a3,a4,a5,a6,a7;                           
output [`bw-1:0] do;    

reg [`bw-1:0] a0,a0_d,a1,a1_d,a2,a3,a4,a5,a6,a7;
always @(posedge clk or negedge nrst)
 if (~nrst)
  begin
    a0<=0; a1<=0; a2<=0; a3<=0;
    a4<=0; a5<=0; a6<=0; a7<=0;
  end
   else begin //2 4 5 7 在 idct 时空着
  if (a0en)       a0  <=di;
  if (a1en)       a1  <=di;
  if (a2en&dcten) a2  <=di;
  if (a3en)       a3  <=di;
  if (a4en)       a4  <=di; // 当idct 输出 m2
  if (a5en)       a5  <=di; // 当idct 输出 m1
  if (a6en)       a6  <=di;
  if (a7en&dcten) a7  <=di; 
  if (a0en)       a0_d<=a0; 
  if (a1en)       a1_d<=a1; 
 end

wire [`bw-1:0] sub_a1=dcten? (sub1en? a3:
                              sub2en? a2:
                              sub3en? a1_d:
                              sub4en? a0_d:0):
                      idcten?(sub1en? a3:       
                              sub2en? 0 :      
                              sub3en? a1:     
                              sub4en? a0:0):0;    
                      
wire [`bw-1:0] sub_a2=dcten? (sub1en? a7:     //idcten?(sub1en? 0 :      
                              sub2en? a6:     //       (sub2en? a6:      
                              sub3en? a5:     //       (sub3en? 0 :      
                              sub4en? a4:0):  //       (sub4en? 0 :0):0; 
                                              // 化简后可得 
                      idcten?(sub2en? a6:0):0;      
                                                                                       
wire [`bw-1:0] bseries;                      

sub sub(.a1(sub_a1), .a2(sub_a2), .sum(bseries));
//bseries then fed into the register...

 
reg  [`bw-1:0] sccreg1, sccreg2, sccreg3, sccreg4;
wire [`bw-1:0] sccreg_in=scc4en? bseries:(~sccreg4+1);

wire sccreg1en= scc4en | scc4en_d;
always @(posedge clk or negedge nrst)
 if (~nrst)         sccreg1<=0;
 else if (sccreg1en)sccreg1<=sccreg_in;
 
always @(posedge clk or negedge nrst)
 if (~nrst)         sccreg2<=0; 
 else if (scc4en_d) sccreg2<=sccreg1;
 
always @(posedge clk or negedge nrst)
 if (~nrst)    sccreg3<=0;   
 else          sccreg3<=sccreg2;
 
always @(posedge clk or negedge nrst)
 if (~nrst)    sccreg4<=0;
 else          sccreg4<=sccreg3;
//==============================================================================================================
// multiplier part 
//0.5 multiplier 
wire [`bw-1:0] c0=(sccreg1[`bw-1]==1)? {1'b1,sccreg1[`bw-1:1]}:{1'b0,sccreg1[`bw-1:1]};
 
//0.415734 multiplier 0.10-10_1010_1             0.0110_1010_0110110
wire [`bw+3:0] csa041_tmp;
wire [`bw-1:0] csa6_2=(sccreg2[`bw-1]==1)?{2'b0,~sccreg2[`bw-1:2]}:{  2'b11,~sccreg2[`bw-1:2]}; //-2 次方是负的
wire [`bw-1:0] csa6_3=(sccreg2[`bw-1]==1)?{{4{1'b1}},sccreg2[`bw-1:4]}:{ 4'b0,sccreg2[`bw-1:4]};  
wire [`bw-1:0] csa6_4=(sccreg2[`bw-1]==1)?{{6{1'b1}},sccreg2[`bw-1:6]}:{ 6'b0,sccreg2[`bw-1:6]};  
wire [`bw-1:0] csa6_5=(sccreg2[`bw-1]==1)?{{8{1'b1}},sccreg2[`bw-1:8]}:{ 8'b0,sccreg2[`bw-1:8]};
csa6 csa6(.a1(sccreg2), .a2(csa6_2), .a3(csa6_3), .a4(csa6_4), .a5(csa6_5), .a6({11'b0,1'b1}), .sum(csa041_tmp) );
//wire [`bw-1:0] csa041=csa041_tmp[`bw:1];       
wire [`bw:0] csa041=csa041_tmp[`bw:0];  

//-0.097545 multiplier -0.0010_-1001_0000_-1  -0.0001_1000_1111_100
wire [`bw+2:0] csa009_tmp;
wire [`bw-1:0] csa4_2=(sccreg3[`bw-1]==1)?{2'b0,~sccreg3[`bw-1:2]}:{  2'b11,~sccreg3[`bw-1:2]}; //-2 次方是负的    
wire [`bw-1:0] csa4_3=(sccreg3[`bw-1]==1)?{{5{1'b1}},sccreg3[`bw-1:5]}:{ 5'b0,sccreg3[`bw-1:5]};
wire [`bw-1:0] csa4_4=(sccreg3[`bw-1]==1)?{10'b0,~sccreg3[`bw-1:10]}:{{10{1'b1}},~sccreg3[`bw-1:10]}; //-2 次方是负的
csa5 csa51(.a1(sccreg3), .a2(csa4_2), .a3(csa4_3), .a4({10'b0,2'b10}), .a5(csa4_4), .sum(csa009_tmp));
//wire [`bw-1:0] csa009=(csa009_tmp[`bw+1]==1)?{1'b1,csa009_tmp[`bw+1:3]}:{1'b0,csa009_tmp[`bw+1:3]};
wire [`bw:0] csa009=(csa009_tmp[`bw+2]==1)?{2'b11,csa009_tmp[`bw+1:2]}:{2'b0,csa009_tmp[`bw+1:2]}; 

  
//0.277785 multiplier 0.0100_100-1_0010         0.0100_0111_0001_110
wire [`bw+2:0] csa027_tmp;                                                                                                                                                              
wire [`bw-1:0] csa5_2=(sccreg4[`bw-1]==1)?{{3{1'b1}}, sccreg4[`bw-1:3]}:{ 3'b0,sccreg4[`bw-1:3]}; //-3 次方是负的                                                                        
wire [`bw-1:0] csa5_3=(sccreg4[`bw-1]==1)?{{6{1'b0}},~sccreg4[`bw-1:6]}:{{6{1'b1}},~sccreg4[`bw-1:6]};                   
wire [`bw-1:0] csa5_4=(sccreg4[`bw-1]==1)?{{9{1'b1}},sccreg4[`bw-1:9]}:{ 9'b0,sccreg4[`bw-1:9]};
csa5 csa52(.a1(sccreg4), .a2(csa5_2), .a3(csa5_3), .a4(csa5_4), .a5({11'b0,1'b1}), .sum(csa027_tmp) );
wire [`bw:0] csa027=csa027_tmp[`bw+1:1];  

wire [`bw+3:0] do_tmp;
wire [`bw-1:0] do=do_tmp[`bw:1];
csa52 csa53(.a1({c0,1'b0}), .a2(csa041), .a3(~csa009), .a4(csa027), .a5({11'b0,2'b10}), .sum(do_tmp));

//wire [`bw+1:0] test={c0,2'b0}+csa041_tmp+csa009_tmp+csa027_tmp+1;
//wire [`bw+1:0] test1=test[`bw+1:1];
//wire [`bw:0] test2=test[`bw+1:2];

endmodule