📄 iic.v
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module iic(scl,
sda,
reset,
clk, //local high-rate clk
LDPC_reg,
QAM_reg,
Interleave_reg,
Carrier_reg,
Pilot_reg,
Phase_rotation_reg,
PN_length_reg,
Test_reg,
Reset_reg,
out_flag ,
tst_scl,
tst_sda,
tst_scl_tmp,
tst_ff,
tst_w_r,
tst_LDPC ,
// j ,
det_sta,
det_stop,
tst_addr,
tst_data ,
// over ,
Delay_h,
Delay_m,
Delay_l,
sfn
);
input scl;
input sda;
input reset;
input clk;
//output over;
output[1:0] LDPC_reg;
output[2:0] QAM_reg;
output Interleave_reg;
output Carrier_reg;
output Pilot_reg;
output Phase_rotation_reg;
output[1:0] PN_length_reg;
output Test_reg;
output Reset_reg;
output[7:0] Delay_h,Delay_m,Delay_l;
output tst_sda;
output tst_scl;
output tst_scl_tmp;
output tst_ff;
output tst_w_r;
output[1:0] tst_LDPC;
//output[4:0]j;
output out_flag,det_sta,det_stop; //used for tst module
output[7:0] tst_addr;
output[7:0] tst_data;
output sfn;
wire clk,reset;
reg[7:0] data_buf;
reg[7:0] sda_buf;
reg[7:0] addr_byte,addr_byte_buf;
reg[1:0] d_state;
reg[1:0] LDPC_reg;
reg[2:0] QAM_reg;
reg Interleave_reg;
reg Carrier_reg;
reg Pilot_reg;
reg Phase_rotation_reg;
reg[1:0] PN_length_reg;
reg Test_reg;
reg Reset_reg;
reg[7:0] Delay_h,Delay_m,Delay_l;
reg sfn;
reg sda_tmp;
reg flag1,flag1_1,flag1_2,flag1_3;
reg flag2,flag2_1,flag2_2,flag2_3;
reg flag3,flag3_1,flag3_2;
reg flag4,flag4_1,flag4_2;
reg ff_w,ff_r;
//reg w_r;
reg scl_tmp;
reg clk_use;
reg[4:0] i,j,k,m;
//-------------------------------------------------------------
parameter r8=8'b10000001, w8=8'b10000000,
r7=8'b10000011, w7=8'b10000010,
r6=8'b10000101, w6=8'b10000100,
r5=8'b10000111, w5=8'b10000110,
r4=8'b10001001, w4=8'b10001000,
r3=8'b10001011, w3=8'b10001010,
r2=8'b10001101, w2=8'b10001100,
r1=8'b10001111, w1=8'b10001110,
r0=8'b10010001, w0=8'b10010000,
w9=8'b10010010, //delay_h
w10=8'b10010100, //delay_m
w11=8'b10010110, //delay_l
w12=8'b10011000;
parameter d_idle=2'd0,
sda_h2l=2'd1,
sda_l2h=2'd2,
gen=2'd3;
//-------------------------------------------------------------
assign tst_sda =sda;
assign tst_scl =scl;
assign tst_scl_tmp =tst_scl_tmp;
assign tst_w_r =0;//w_r;
assign tst_LDPC =LDPC_reg;
wire[4:0] tst_i =i;
wire[4:0] tst_j =j;
wire[4:0] tst_k =k;
wire[4:0] tst_m =m;
assign tst_addr =addr_byte ;
assign tst_data =data_buf;
reg out_flag;
////zz/////assign sda=(out_flag==1)?1'b0:1'bz;//if used for tst ,it is out_flag;if else ,ff is must.
//assign ff=(w_r)? ff_w :ff_r; //w_r=1 host2slave;w_r=0 slave2host
/*
always@(posedge clk or negedge reset)
if(!reset)
begin
clk_use<=0;
m<=0;
end
else
begin
if(m==23)
begin
clk_use<=~clk_use;
m<=0;
end
else
m<=m+1;
end
//------------------detect------------------------------
always@(posedge clk_use or negedge reset) //clk_use
if(!reset)
begin
det_sta<=0;
det_stop<=0;
d_state<=d_idle;
end
else
case(d_state)
d_idle:
begin
if(scl)
begin
if(sda)
d_state<=sda_l2h;
else
d_state<=sda_h2l;
end
else ;
end
sda_h2l:
begin
if(!scl)
d_state<=d_idle;
else if(sda)
begin
d_state<=gen;
det_stop<=1;
end
else
;
end
sda_l2h:
begin
if(!scl)
d_state<=d_idle;
else if(!sda)
begin
d_state<=gen;
det_sta<=1;
end
else
;
end
gen :
begin
d_state<=d_idle;
det_sta<=0;
det_stop<=0;
end
default:
begin
det_sta<=0;
det_stop<=0;
d_state<=d_idle;
end
endcase
//------------------------------------------------------
*/
reg ready,over;
always @(negedge reset or negedge sda)
if(!reset)
ready<=0;
else if(scl&&(j<=5))
ready<=1;
else
ready<=0;
always@(negedge reset or posedge sda)
if(!reset)
over<=1;
else if(scl)
over<=1;
else
over<=0;
wire start=ready|(~over);
wire det_sta=start;
wire det_stop=ready;
always@(posedge scl or negedge start or negedge reset)
if(!reset)
j<=0;
else
if(!start)
j<=0;
else
if(j<=21)
j<=j+1'b1;
else
;
//always@(negedge scl_tmp or posedge det_sta)
//if(det_sta)
// i<=0;
//else
// begin
// if(i==21)
// i<=0;
// else
// i<=i+1;
// end
//
//always@(posedge clk or posedge det_sta) //clk_use
//if(det_sta)
// begin
// flag1 <=0;
// flag1_1 <=0;
// flag1_2 <=0;
// flag1_3 <=0;
// flag2 <=0;
// flag2_1 <=0;
// flag2_2 <=0;
// flag2_3 <=0;
// scl_tmp<=0;
// k<=1;
// end
//else
// begin
// if (j==8||j==17)
// flag1<=1'b1;
// else
// flag1<=1'b0;
//
// flag1_1<=flag1;
// flag1_2<=flag1_1;
// flag1_3<=flag1_2;
//
// if (j==10||j==19)
// flag2<=1'b1;
// else
// flag2<=1'b0;
//
// flag2_1<=flag2;
// flag2_2<=flag2_1;
// flag2_3<=flag2_2;
//
// if(j==19)
// flag3<=1'b1;
// else
// flag3<=1'b0;
//
// flag3_1<=flag3;
// flag3_2<=flag3_1;
//
// if(j==10)
// flag4<=1'b1;
// else
// flag4<=1'b0;
//
// flag4_1<=flag4;
// flag4_2<=flag4_1;
//
//
// if (k==4)
// begin
// scl_tmp<=~scl_tmp;
// k<=0;
// end
// else
// k<=k+1;
// if (i==21)
// k<=0;
//
// end
//wire rst1=!reset|flag2_2;
////---------------
//always@(negedge flag1_2 or posedge rst1)
//begin
//if(flag1_2==0)
// ff_r<=1;
//
//if(rst1)
// ff_r<=0;
//
//end
//
//wire rst2=!reset|flag3_2;
//always@(negedge flag1_2 or posedge rst2)
//begin
//if(flag1_2==0)
// ff_w<=1;
//
//if(rst2)
// ff_w<=0;
//end
//
always@(posedge scl or negedge start)
if(!start)
begin
out_flag <=0;
// LDPC_reg <=2'b00;
// QAM_reg <=3'b001;
// Interleave_reg <=1'b1;
// Carrier_reg <=1'b0;
// Pilot_reg <=1'b0;
// Phase_rotation_reg <=1'b1;
// PN_length_reg <=2'b00;
// Test_reg <=1'b0;
// Reset_reg <=1'b0;
addr_byte_buf <=0;
data_buf <=0;
end
else
begin
case(j)
0: begin addr_byte_buf[7]<=sda; out_flag<=0; end
1: begin addr_byte_buf[6]<=sda; out_flag<=0; end
2: begin addr_byte_buf[5]<=sda; out_flag<=0; end
3: begin addr_byte_buf[4]<=sda; out_flag<=0; end
4: begin addr_byte_buf[3]<=sda; out_flag<=0; end
5: begin addr_byte_buf[2]<=sda; out_flag<=0; end
6: begin addr_byte_buf[1]<=sda; out_flag<=0; end
7: begin addr_byte_buf[0]<=sda; out_flag<=0; end
8: begin addr_byte<=addr_byte_buf; out_flag<=1; end
// 9: begin out_flag<=0; end
9: begin data_buf[7]<=sda; out_flag<=0; end
10: begin data_buf[6]<=sda; out_flag<=0; end
11: begin data_buf[5]<=sda; out_flag<=0; end
12: begin data_buf[4]<=sda; out_flag<=0; end
13: begin data_buf[3]<=sda; out_flag<=0; end
14: begin data_buf[2]<=sda; out_flag<=0; end
15: begin data_buf[1]<=sda; out_flag<=0; end
16: begin data_buf[0]<=sda; out_flag<=1; end
17: begin read_from_host; out_flag<=0; end
//18
default: out_flag<=0;
endcase
end
task read_from_host;
begin
casex(addr_byte)
w8: LDPC_reg<=data_buf[1:0];
w7: QAM_reg<=data_buf[2:0];
w6: Interleave_reg<=data_buf[0];
w5: Carrier_reg<=data_buf[0];
w4: Pilot_reg<=data_buf[0];
w3: Phase_rotation_reg<=data_buf[0];
w2: PN_length_reg<=data_buf[1:0];
w1: Test_reg<=data_buf[0];
w0: Reset_reg<=data_buf[0];
w9: Delay_h <=data_buf;
w10: Delay_m <=data_buf;
w11: Delay_l <=data_buf;
w12: sfn <=data_buf[0];
endcase
end
endtask
//always@(posedge flag4_2 or posedge det_sta)
//if(det_sta)
// sda_buf<=0;
//else
// begin
// casex(addr_byte)
// r8: sda_buf <={6'd0,LDPC_reg};
// r7: sda_buf <={5'd0,QAM_reg};
// r6: sda_buf <={7'd0,Interleave_reg};
// r5: sda_buf <={7'd0,Carrier_reg};
// r4: sda_buf <={7'd0,Pilot_reg};
// r3: sda_buf <={7'd0,Phase_rotation_reg};
// r2: sda_buf <={6'd0,PN_length_reg};
// r1: sda_buf <={7'd0,Test_reg};
// r0: sda_buf <={7'd0,Reset_reg};
// default:sda_buf <=0;
// endcase
// end
//always@(posedge scl_tmp or posedge det_sta)
//if(det_sta)
// sda_tmp<=0;
//else
//begin
// case(i)
// 9: sda_tmp <=sda_buf[7];
// 10: sda_tmp <=sda_buf[6];
// 11: sda_tmp <=sda_buf[5];
// 12: sda_tmp <=sda_buf[4];
// 13: sda_tmp <=sda_buf[3];
// 14: sda_tmp <=sda_buf[2];
// 15: sda_tmp <=sda_buf[1];
// 16: sda_tmp <=sda_buf[0];
// //17: sda_tmp <=sda_buf[0];
// default:sda_tmp <=0;
// endcase
//end
//
endmodule
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