jpeg_idctb.v

jpeg格式到bmp格式的硬件实现

//---------------------------------------------------------------------------
// File Name   : jpeg_idctb.v
// Module Name : jpeg_idctb
// Description : data register for iDCT
// Project     : JPEG Decoder
// Belong to   : 
// Author      : H.Ishihara
// E-Mail      : [e-mail]
// HomePage    : http://www.sweetcafe.jp/
// Date        : 2006/10/01
// Rev.        : 1.1
//---------------------------------------------------------------------------
// Rev. Date       Description
//---------------------------------------------------------------------------
// 1.01 2006/10/01 1st Release
//---------------------------------------------------------------------------
// $Id: 
//---------------------------------------------------------------------------
`timescale 1ps / 1ps

module jpeg_idctb
  (
   rst,
   clk,

   DataInEnable,
   DataInPage,
   DataInCount,
   DataInIdle,
   Data0In,
   Data1In,

   DataOutEnable,
   DataOutSel,
   Data00Out,
   Data01Out,
   Data02Out,
   Data03Out,
   Data04Out,
   Data05Out,
   Data06Out,
   Data07Out,
   Data08Out,
   Data09Out,
   Data10Out,
   Data11Out,
   Data12Out,
   Data13Out,
   Data14Out,
   Data15Out,
   Data16Out,
   Data17Out,
   Data18Out,
   Data19Out,
   Data20Out,
   Data21Out,
   Data22Out,
   Data23Out,
   Data24Out,
   Data25Out,
   Data26Out,
   Data27Out,
   Data28Out,
   Data29Out,
   Data30Out,
   Data31Out,
   Data32Out,
   Data33Out,
   Data34Out,
   Data35Out,
   Data36Out,
   Data37Out,
   Data38Out,
   Data39Out,
   Data40Out,
   Data41Out,
   Data42Out,
   Data43Out,
   Data44Out,
   Data45Out,
   Data46Out,
   Data47Out,
   Data48Out,
   Data49Out,
   Data50Out,
   Data51Out,
   Data52Out,
   Data53Out,
   Data54Out,
   Data55Out,
   Data56Out,
   Data57Out,
   Data58Out,
   Data59Out,
   Data60Out,
   Data61Out,
   Data62Out,
   Data63Out,

   BankARelease,
   BankBRelease
   );

   input clk;
   input rst;

   input DataInEnable;
   input [2:0] DataInPage;
   input [1:0] DataInCount;
   output      DataInIdle;
   input [15:0] Data0In;
   input [15:0] Data1In;

   output       DataOutEnable;
   input         DataOutSel;
   output [15:0] Data00Out;
   output [15:0] Data01Out;
   output [15:0] Data02Out;
   output [15:0] Data03Out;
   output [15:0] Data04Out;
   output [15:0] Data05Out;
   output [15:0] Data06Out;
   output [15:0] Data07Out;
   output [15:0] Data08Out;
   output [15:0] Data09Out;
   output [15:0] Data10Out;
   output [15:0] Data11Out;
   output [15:0] Data12Out;
   output [15:0] Data13Out;
   output [15:0] Data14Out;
   output [15:0] Data15Out;
   output [15:0] Data16Out;
   output [15:0] Data17Out;
   output [15:0] Data18Out;
   output [15:0] Data19Out;
   output [15:0] Data20Out;
   output [15:0] Data21Out;
   output [15:0] Data22Out;
   output [15:0] Data23Out;
   output [15:0] Data24Out;
   output [15:0] Data25Out;
   output [15:0] Data26Out;
   output [15:0] Data27Out;
   output [15:0] Data28Out;
   output [15:0] Data29Out;
   output [15:0] Data30Out;
   output [15:0] Data31Out;
   output [15:0] Data32Out;
   output [15:0] Data33Out;
   output [15:0] Data34Out;
   output [15:0] Data35Out;
   output [15:0] Data36Out;
   output [15:0] Data37Out;
   output [15:0] Data38Out;
   output [15:0] Data39Out;
   output [15:0] Data40Out;
   output [15:0] Data41Out;
   output [15:0] Data42Out;
   output [15:0] Data43Out;
   output [15:0] Data44Out;
   output [15:0] Data45Out;
   output [15:0] Data46Out;
   output [15:0] Data47Out;
   output [15:0] Data48Out;
   output [15:0] Data49Out;
   output [15:0] Data50Out;
   output [15:0] Data51Out;
   output [15:0] Data52Out;
   output [15:0] Data53Out;
   output [15:0] Data54Out;
   output [15:0] Data55Out;
   output [15:0] Data56Out;
   output [15:0] Data57Out;
   output [15:0] Data58Out;
   output [15:0] Data59Out;
   output [15:0] Data60Out;
   output [15:0] Data61Out;
   output [15:0] Data62Out;
   output [15:0] Data63Out;

   input         BankARelease;
   input         BankBRelease;
   
   reg           BankAEnable;
   reg           BankBEnable;
   reg           DataInBank;
   
   always @(posedge clk or negedge rst) begin
      if(!rst) begin
         BankAEnable <= 1'b0;
         BankBEnable <= 1'b0;
         DataInBank  <= 1'b0;
      end else begin
         if(BankAEnable == 1'b0 & DataInBank == 1'b0) begin
            if(DataInEnable == 1'b1 & 
               DataInPage == 3'd7 & DataInCount == 2'd3) begin
               BankAEnable <= 1'b1;
            end
         end else begin
            if(BankARelease == 1'b1) begin
               BankAEnable <= 1'b0;
            end
         end
         if(BankBEnable == 1'b0 & DataInBank == 1'b1) begin
            if(DataInEnable == 1'b1 & 
               DataInPage == 3'd7 & DataInCount == 2'd3) begin
               BankBEnable <= 1'b1;
            end
         end else begin
            if(BankBRelease == 1'b1) begin
               BankBEnable <= 1'b0;
            end
         end
         if(DataInEnable == 1'b1 & 
            DataInPage == 3'd7 & DataInCount == 2'd3) begin
            DataInBank   <= ~DataInBank;
         end
      end // else: !if(!rst)
   end // always @ (posedge clk or negedge rst)

   assign DataInIdle = BankAEnable == 1'b0 | BankBEnable == 1'b0;

   assign DataOutEnable = DataInEnable == 1'b1 & DataInPage == 3'b111 &
                          DataInCount  == 2'b11;
   
   reg [15:0] BankAReg [0:63];
   
   always @(posedge clk or negedge rst) begin
      if(!rst) begin
         BankAReg[0] <= 12'h000;
         BankAReg[1] <= 12'h000;
         BankAReg[2] <= 12'h000;
         BankAReg[3] <= 12'h000;
         BankAReg[4] <= 12'h000;
         BankAReg[5] <= 12'h000;
         BankAReg[6] <= 12'h000;
         BankAReg[7] <= 12'h000;
         BankAReg[8] <= 12'h000;
         BankAReg[9] <= 12'h000;
         BankAReg[10] <= 12'h000;
         BankAReg[11] <= 12'h000;
         BankAReg[12] <= 12'h000;
         BankAReg[13] <= 12'h000;
         BankAReg[14] <= 12'h000;
         BankAReg[15] <= 12'h000;
         BankAReg[16] <= 12'h000;
         BankAReg[17] <= 12'h000;
         BankAReg[18] <= 12'h000;
         BankAReg[19] <= 12'h000;
         BankAReg[20] <= 12'h000;
         BankAReg[21] <= 12'h000;
         BankAReg[22] <= 12'h000;
         BankAReg[23] <= 12'h000;
         BankAReg[24] <= 12'h000;
         BankAReg[25] <= 12'h000;
         BankAReg[26] <= 12'h000;
         BankAReg[27] <= 12'h000;
         BankAReg[28] <= 12'h000;
         BankAReg[29] <= 12'h000;
         BankAReg[30] <= 12'h000;
         BankAReg[31] <= 12'h000;
         BankAReg[32] <= 12'h000;
         BankAReg[33] <= 12'h000;
         BankAReg[34] <= 12'h000;
         BankAReg[35] <= 12'h000;
         BankAReg[36] <= 12'h000;
         BankAReg[37] <= 12'h000;
         BankAReg[38] <= 12'h000;
         BankAReg[39] <= 12'h000;
         BankAReg[40] <= 12'h000;
         BankAReg[41] <= 12'h000;
         BankAReg[42] <= 12'h000;
         BankAReg[43] <= 12'h000;
         BankAReg[44] <= 12'h000;
         BankAReg[45] <= 12'h000;
         BankAReg[46] <= 12'h000;
         BankAReg[47] <= 12'h000;
         BankAReg[48] <= 12'h000;
         BankAReg[49] <= 12'h000;
         BankAReg[50] <= 12'h000;
         BankAReg[51] <= 12'h000;
         BankAReg[52] <= 12'h000;
         BankAReg[53] <= 12'h000;
         BankAReg[54] <= 12'h000;
         BankAReg[55] <= 12'h000;
         BankAReg[56] <= 12'h000;
         BankAReg[57] <= 12'h000;
         BankAReg[58] <= 12'h000;
         BankAReg[59] <= 12'h000;
         BankAReg[60] <= 12'h000;
         BankAReg[61] <= 12'h000;
         BankAReg[62] <= 12'h000;
         BankAReg[63] <= 12'h000;
      end else begin // if (!rst)
         if(DataInEnable == 1'b1 & DataInBank == 1'b0) begin
            case(DataInPage)
              3'd0: begin
                 case(DataInCount)
                   2'd0: begin
                      BankAReg[0] <= Data0In;
                      BankAReg[7] <= Data1In;
                   end
                   2'd1: begin
                      BankAReg[1] <= Data0In;
                      BankAReg[6] <= Data1In;
                   end
                   2'd2: begin
                      BankAReg[2] <= Data0In;
                      BankAReg[5] <= Data1In;
                   end
                   2'd3: begin
                      BankAReg[3] <= Data0In;
                      BankAReg[4] <= Data1In;
                   end
                 endcase // case(DataInCount)
              end // case: 3'd0
              3'd1: begin
                 case(DataInCount)
                   2'd0: begin
                      BankAReg[8] <= Data0In;
                      BankAReg[15] <= Data1In;
                   end
                   2'd1: begin
                      BankAReg[9] <= Data0In;
                      BankAReg[14] <= Data1In;
                   end
                   2'd2: begin
                      BankAReg[10] <= Data0In;
                      BankAReg[13] <= Data1In;
                   end
                   2'd3: begin
                      BankAReg[11] <= Data0In;
                      BankAReg[12] <= Data1In;
                   end
                 endcase // case(DataInCount)
              end // case: 3'd1
              3'd2: begin
                 case(DataInCount)
                   2'd0: begin
                      BankAReg[16] <= Data0In;
                      BankAReg[23] <= Data1In;
                   end
                   2'd1: begin
                      BankAReg[17] <= Data0In;
                      BankAReg[22] <= Data1In;
                   end
                   2'd2: begin
                      BankAReg[18] <= Data0In;
                      BankAReg[21] <= Data1In;
                   end
                   2'd3: begin
                      BankAReg[19] <= Data0In;
                      BankAReg[20] <= Data1In;
                   end
                 endcase // case(DataInCount)
              end // case: 3'd2
              3'd3: begin
                 case(DataInCount)
                   2'd0: begin
                      BankAReg[24] <= Data0In;
                      BankAReg[31] <= Data1In;
                   end
                   2'd1: begin
                      BankAReg[25] <= Data0In;
                      BankAReg[30] <= Data1In;
                   end
                   2'd2: begin
                      BankAReg[26] <= Data0In;
                      BankAReg[29] <= Data1In;
                   end
                   2'd3: begin
                      BankAReg[27] <= Data0In;
                      BankAReg[28] <= Data1In;
                   end
                 endcase // case(DataInCount)
              end // case: 3'd3
              3'd4: begin
                 case(DataInCount)
                   2'd0: begin
                      BankAReg[32] <= Data0In;
                      BankAReg[39] <= Data1In;
                   end