jpeg_ziguzagu.v

jpeg格式到bmp格式的硬件实现

//---------------------------------------------------------------------------
// File Name   : jpeg_ziguzagu.v
// Module Name : jpeg_ziguzagu
// Description : Ziguzagu
// Project     : JPEG Decoder
// Belong to   : 
// Author      : H.Ishihara
// E-Mail      : [e-mail]
// HomePage    : http://www.sweetcafe.jp/
// Date        : 2006/10/01
// Rev.        : 1.1
//---------------------------------------------------------------------------
// Rev. Date       Description
//---------------------------------------------------------------------------
// 1.01 2006/10/01 1st Release
//---------------------------------------------------------------------------
// $Id: 
//---------------------------------------------------------------------------
`timescale 1ps / 1ps

module jpeg_ziguzagu
  (
   rst,
   clk,

   DataInEnable,
   DataInAddress,
   DataInColor,
   DataInIdle,
   DataIn,

   HaffumanEndEnable,

   DataOutEnable,
   DataOutColor,
   DataOutSel,
   Data00Reg,
   Data01Reg,
   Data02Reg,
   Data03Reg,
   Data04Reg,
   Data05Reg,
   Data06Reg,
   Data07Reg,
   Data08Reg,
   Data09Reg,
   Data10Reg,
   Data11Reg,
   Data12Reg,
   Data13Reg,
   Data14Reg,
   Data15Reg,
   Data16Reg,
   Data17Reg,
   Data18Reg,
   Data19Reg,
   Data20Reg,
   Data21Reg,
   Data22Reg,
   Data23Reg,
   Data24Reg,
   Data25Reg,
   Data26Reg,
   Data27Reg,
   Data28Reg,
   Data29Reg,
   Data30Reg,
   Data31Reg,
   Data32Reg,
   Data33Reg,
   Data34Reg,
   Data35Reg,
   Data36Reg,
   Data37Reg,
   Data38Reg,
   Data39Reg,
   Data40Reg,
   Data41Reg,
   Data42Reg,
   Data43Reg,
   Data44Reg,
   Data45Reg,
   Data46Reg,
   Data47Reg,
   Data48Reg,
   Data49Reg,
   Data50Reg,
   Data51Reg,
   Data52Reg,
   Data53Reg,
   Data54Reg,
   Data55Reg,
   Data56Reg,
   Data57Reg,
   Data58Reg,
   Data59Reg,
   Data60Reg,
   Data61Reg,
   Data62Reg,
   Data63Reg,

   BankARelease,
   BankBRelease
   );

   input         clk;
   input         rst;

   input 	 DataInEnable;
   input [5:0] 	 DataInAddress;
   input [2:0] 	 DataInColor;
   output 	 DataInIdle;
   input [15:0]  DataIn;

   input 	 HaffumanEndEnable;

   output 	 DataOutEnable;
   output [2:0]	 DataOutColor;
   input 	 DataOutSel;
   output [15:0] Data00Reg;
   output [15:0] Data01Reg;
   output [15:0] Data02Reg;
   output [15:0] Data03Reg;
   output [15:0] Data04Reg;
   output [15:0] Data05Reg;
   output [15:0] Data06Reg;
   output [15:0] Data07Reg;
   output [15:0] Data08Reg;
   output [15:0] Data09Reg;
   output [15:0] Data10Reg;
   output [15:0] Data11Reg;
   output [15:0] Data12Reg;
   output [15:0] Data13Reg;
   output [15:0] Data14Reg;
   output [15:0] Data15Reg;
   output [15:0] Data16Reg;
   output [15:0] Data17Reg;
   output [15:0] Data18Reg;
   output [15:0] Data19Reg;
   output [15:0] Data20Reg;
   output [15:0] Data21Reg;
   output [15:0] Data22Reg;
   output [15:0] Data23Reg;
   output [15:0] Data24Reg;
   output [15:0] Data25Reg;
   output [15:0] Data26Reg;
   output [15:0] Data27Reg;
   output [15:0] Data28Reg;
   output [15:0] Data29Reg;
   output [15:0] Data30Reg;
   output [15:0] Data31Reg;
   output [15:0] Data32Reg;
   output [15:0] Data33Reg;
   output [15:0] Data34Reg;
   output [15:0] Data35Reg;
   output [15:0] Data36Reg;
   output [15:0] Data37Reg;
   output [15:0] Data38Reg;
   output [15:0] Data39Reg;
   output [15:0] Data40Reg;
   output [15:0] Data41Reg;
   output [15:0] Data42Reg;
   output [15:0] Data43Reg;
   output [15:0] Data44Reg;
   output [15:0] Data45Reg;
   output [15:0] Data46Reg;
   output [15:0] Data47Reg;
   output [15:0] Data48Reg;
   output [15:0] Data49Reg;
   output [15:0] Data50Reg;
   output [15:0] Data51Reg;
   output [15:0] Data52Reg;
   output [15:0] Data53Reg;
   output [15:0] Data54Reg;
   output [15:0] Data55Reg;
   output [15:0] Data56Reg;
   output [15:0] Data57Reg;
   output [15:0] Data58Reg;
   output [15:0] Data59Reg;
   output [15:0] Data60Reg;
   output [15:0] Data61Reg;
   output [15:0] Data62Reg;
   output [15:0] Data63Reg;
   input         BankARelease;
   input         BankBRelease;
   
   reg           BankAEnable;
   reg           BankBEnable;
   reg           DataInBank;

   reg [2:0] 	 BankAColor;
   reg [2:0] 	 BankBColor;
   
   always @(posedge clk or negedge rst) begin
      if(!rst) begin
         BankAEnable <= 1'b0;
         BankBEnable <= 1'b0;
	 BankAColor  <= 3'b000;
	 BankBColor  <= 3'b000;
         DataInBank  <= 1'b0;
      end else begin
         if(BankAEnable == 1'b0 & DataInBank == 1'b0) begin
            if(HaffumanEndEnable == 1'b1 & DataInIdle == 1'b1) begin
               BankAEnable <= 1'b1;
	       BankAColor  <= DataInColor;
            end
         end else begin
            if(BankARelease == 1'b1) begin
               BankAEnable <= 1'b0;
            end
         end
         if(BankBEnable == 1'b0 & DataInBank == 1'b1) begin
            if(HaffumanEndEnable == 1'b1 & DataInIdle == 1'b1) begin
               BankBEnable <= 1'b1;
	       BankBColor  <= DataInColor;
            end
         end else begin
            if(BankBRelease == 1'b1) begin
               BankBEnable <= 1'b0;
            end
         end
         if(HaffumanEndEnable == 1'b1) begin
            DataInBank   <= ~DataInBank;
         end
      end // else: !if(!rst)
   end // always @ (posedge clk or negedge rst)

   assign DataInIdle = BankAEnable == 1'b0 | BankBEnable == 1'b0;
   assign DataOutEnable = BankAEnable == 1'b1 | BankBEnable == 1'b1;
   assign DataOutColor  = (DataInBank)?BankBColor:BankAColor;

   wire   ZigAEnable;
   wire   ZigBEnable;
   
   wire [15:0] BankA00Reg;
   wire [15:0] BankA01Reg;
   wire [15:0] BankA02Reg;
   wire [15:0] BankA03Reg;
   wire [15:0] BankA04Reg;
   wire [15:0] BankA05Reg;
   wire [15:0] BankA06Reg;
   wire [15:0] BankA07Reg;
   wire [15:0] BankA08Reg;
   wire [15:0] BankA09Reg;
   wire [15:0] BankA10Reg;
   wire [15:0] BankA11Reg;
   wire [15:0] BankA12Reg;
   wire [15:0] BankA13Reg;
   wire [15:0] BankA14Reg;
   wire [15:0] BankA15Reg;
   wire [15:0] BankA16Reg;
   wire [15:0] BankA17Reg;
   wire [15:0] BankA18Reg;
   wire [15:0] BankA19Reg;
   wire [15:0] BankA20Reg;
   wire [15:0] BankA21Reg;
   wire [15:0] BankA22Reg;
   wire [15:0] BankA23Reg;
   wire [15:0] BankA24Reg;
   wire [15:0] BankA25Reg;
   wire [15:0] BankA26Reg;
   wire [15:0] BankA27Reg;
   wire [15:0] BankA28Reg;
   wire [15:0] BankA29Reg;
   wire [15:0] BankA30Reg;
   wire [15:0] BankA31Reg;
   wire [15:0] BankA32Reg;
   wire [15:0] BankA33Reg;
   wire [15:0] BankA34Reg;
   wire [15:0] BankA35Reg;
   wire [15:0] BankA36Reg;
   wire [15:0] BankA37Reg;
   wire [15:0] BankA38Reg;
   wire [15:0] BankA39Reg;
   wire [15:0] BankA40Reg;
   wire [15:0] BankA41Reg;
   wire [15:0] BankA42Reg;
   wire [15:0] BankA43Reg;
   wire [15:0] BankA44Reg;
   wire [15:0] BankA45Reg;
   wire [15:0] BankA46Reg;
   wire [15:0] BankA47Reg;
   wire [15:0] BankA48Reg;
   wire [15:0] BankA49Reg;
   wire [15:0] BankA50Reg;
   wire [15:0] BankA51Reg;
   wire [15:0] BankA52Reg;
   wire [15:0] BankA53Reg;
   wire [15:0] BankA54Reg;
   wire [15:0] BankA55Reg;
   wire [15:0] BankA56Reg;