crc-generator.html
来自「一个verilog实现的crc校验」· HTML 代码 · 共 98 行
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<META NAME="description" CONTENT="5x4Gbps CRC Generator designed with standard cells and conceived as an 'IP-less IP' to be used in System-on-a-Chip designs.">
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<TITLE>OPENCORES
project: 5x5Gbps CRC Generator designed with Standard Cells
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<b><font size=+2 color=#bf0000>Project: 5x4Gbps CRC Generator designed with Standard Cells</font></b><p>
<b><font size=+1>Details</font></b> <p>Category: High-Speed Wireline Communications
<br>Last updated: 28/5/2001
<br>Created: 28/5/2001
<br>Stage: Production/Stable
<p><b><font size=+1>Description</font></b>
<p> A 32-bit parallel and highly pipelined Cyclic Redundancy Code (CRC) generator is presented. The design can handle 5 different channels at an input rate of 2Gbps each (the total output throughput is 5x4Gbps.)
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The generated CRCs are compatible with the 32-bit Ethernet standards. The circuit has been implemented with standard cells in a 0.35Micron standard CMOS process using the properties of Galois Fields and has been conceived as a "free" IP.
<p><b><font size=+1>Status</font></b>
<p><ul><li>Stable</li></ul>
<p><b><font size=+1>Downloads</font></b>
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<td valign=top><b>Date</b></td>
<td valign=top><b>Description</b></td>
<td valign=top><b>Link</b></td>
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<tr bgcolor='#ffffff'><td valign=top>15/12/2001</td>
<td valign=top>The paper presented at the IEEE Student Paper Contest in Cairo, Egypt. It shows the main highlights of the design and the algorithm.<br></td>
<td valign=top><a href='./CRC_ie3_contest.pdf'>CRC_ie3_contest.pdf</a></td>
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<tr bgcolor='#f0f0f0'><td valign=top>28/5/2001</td>
<td valign=top>Complete project (documentation, code, testbench). <br></td>
<td valign=top><a href='./CRC-generator.tgz'>CRC-generator.tgz</a></td>
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<tr bgcolor='#f0f0f0'><td valign=top>10/6/2002</td>
<td valign=top>README file. <br></td>
<td valign=top><a href='./README'>README</a></td>
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<font size=+1>Author</font></b> <p><ul><li>Jos⌨️ 快捷键说明
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