gf_multiplier.vhd

来自「一个verilog实现的crc校验」· VHDL 代码 · 共 385 行 · 第 1/2 页

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.all;

entity gf_multiplier is
  
  port (
    reset  : in  std_logic;             -- #RESET
    phi1   : in  std_logic;
    phi2   : in  std_logic;
    input  : in  std_logic_vector(31 downto 0);
                                        -- Input to the Galois Field multiplier. It
                                        -- comes from the feedback of the FCS
    output_fcs : out std_logic_vector(15 downto 0);  -- LS Word 
    -- "inout" to be able to read the signal (feedback)
    output_xor : out std_logic_vector(15 downto 0));   -- MS Word
  
end gf_multiplier;



architecture structural of gf_multiplier is

  -- The output register is half the size of the rest
  component gf_phi1_register_out
    port (
      reset        : in  std_logic;           -- #RESET
      phi1         : in  std_logic;           -- Clock
      input_wip    : in  std_logic_vector(31 downto 0);
      output_final : out std_logic_vector(31 downto 0));
  end component;

  -- These components below are the best example of bad VHDL coding

  component gf_phi1_register_2
    port (
      reset      : in  std_logic;                      -- #RESET
      phi1       : in  std_logic;                      -- Clock
      input_wip  : in  std_logic_vector(31 downto 0);  -- The incoming WIP
      input_fcs  : in  std_logic_vector(31 downto 0);
                    -- The original data for that step. Since we are using pipelining
                    -- we have to grant that we will have the original FCS data
                    -- available.
      output_wip : out std_logic_vector(31 downto 0);
                    -- The modified data -our "WIP"-
      output_fcs : out std_logic_vector(31 downto 0));
                    -- The original data is kept untouched
  end component;

  component gf_phi2_register_3
    port (
      reset      : in  std_logic;                      -- #RESET
      phi2       : in  std_logic;                      -- Clock
      input_wip  : in  std_logic_vector(31 downto 0);  -- The incoming WIP
      input_fcs  : in  std_logic_vector(31 downto 0);
                    -- The original data for that step. Since we are using pipelining
                    -- we have to grant that we will have the original FCS data
                    -- available.
      output_wip : out std_logic_vector(31 downto 0);
                    -- The modified data -our "WIP"-
      output_fcs : out std_logic_vector(31 downto 0));
                    -- The original data is kept untouched
  end component;

  component gf_phi1_register_4
    port (
      reset      : in  std_logic;                      -- #RESET
      phi1       : in  std_logic;                      -- Clock
      input_wip  : in  std_logic_vector(31 downto 0);  -- The incoming WIP
      input_fcs  : in  std_logic_vector(31 downto 0);
                    -- The original data for that step. Since we are using pipelining
                    -- we have to grant that we will have the original FCS data
                    -- available.
      output_wip : out std_logic_vector(31 downto 0);
                    -- The modified data -our "WIP"-
      output_fcs : out std_logic_vector(31 downto 0));
                    -- The original data is kept untouched
  end component;

  component gf_phi2_register_5
    port (
      reset      : in  std_logic;                      -- #RESET
      phi2       : in  std_logic;                      -- Clock
      input_wip  : in  std_logic_vector(31 downto 0);  -- The incoming WIP
      input_fcs  : in  std_logic_vector(31 downto 0);
                    -- The original data for that step. Since we are using pipelining
                    -- we have to grant that we will have the original FCS data
                    -- available.
      output_wip : out std_logic_vector(31 downto 0);
                    -- The modified data -our "WIP"-
      output_fcs : out std_logic_vector(31 downto 0));
                    -- The original data is kept untouched
  end component;

  component gf_phi1_register_6
    port (
      reset      : in  std_logic;                      -- #RESET
      phi1       : in  std_logic;                      -- Clock
      input_wip  : in  std_logic_vector(31 downto 0);  -- The incoming WIP
      input_fcs  : in  std_logic_vector(31 downto 0);
                    -- The original data for that step. Since we are using pipelining
                    -- we have to grant that we will have the original FCS data
                    -- available.
      output_wip : out std_logic_vector(31 downto 0);
                    -- The modified data -our "WIP"-
      output_fcs : out std_logic_vector(31 downto 0));
                    -- The original data is kept untouched
  end component;

  component gf_phi2_register_7
    port (
      reset      : in  std_logic;                      -- #RESET
      phi2       : in  std_logic;                      -- Clock
      input_wip  : in  std_logic_vector(31 downto 0);  -- The incoming WIP
      input_fcs  : in  std_logic_vector(31 downto 0);
                    -- The original data for that step. Since we are using pipelining
                    -- we have to grant that we will have the original FCS data
                    -- available.
      output_wip : out std_logic_vector(31 downto 0);
                    -- The modified data -our "WIP"-
      output_fcs : out std_logic_vector(31 downto 0));
                    -- The original data is kept untouched
  end component;

  component gf_phi1_register_8
    port (
      reset      : in  std_logic;                      -- #RESET
      phi1       : in  std_logic;                      -- Clock
      input_wip  : in  std_logic_vector(31 downto 0);  -- The incoming WIP
      input_fcs  : in  std_logic_vector(31 downto 0);
                    -- The original data for that step. Since we are using pipelining
                    -- we have to grant that we will have the original FCS data
                    -- available.
      output_wip : out std_logic_vector(31 downto 0);
                    -- The modified data -our "WIP"-
      output_fcs : out std_logic_vector(31 downto 0));
                    -- The original data is kept untouched
  end component;

  component gf_phi2_register_9
    port (
      reset      : in  std_logic;                      -- #RESET
      phi2       : in  std_logic;                      -- Clock
      input_wip  : in  std_logic_vector(31 downto 0);  -- The incoming WIP
      input_fcs  : in  std_logic_vector(31 downto 0);
                    -- The original data for that step. Since we are using pipelining
                    -- we have to grant that we will have the original FCS data
                    -- available.
      output_wip : out std_logic_vector(31 downto 0);
                    -- The modified data -our "WIP"-
      output_fcs : out std_logic_vector(31 downto 0));
                    -- The original data is kept untouched
  end component;

  -- These components below are the best example of bad VHDL coding
  
  component gf_xor_2x
    port (
      input_wip  : in  std_logic_vector(31 downto 0);
      input_fcs  : in  std_logic_vector(31 downto 0);
      output_wip : out  std_logic_vector(31 downto 0));
  end component;

  component gf_xor_3x
    port (
      input_wip  : in  std_logic_vector(31 downto 0);
      input_fcs  : in  std_logic_vector(31 downto 0);
      output_wip : out  std_logic_vector(31 downto 0));
  end component;

  component gf_xor_4x
    port (
      input_wip  : in  std_logic_vector(31 downto 0);
      input_fcs  : in  std_logic_vector(31 downto 0);
      output_wip : out  std_logic_vector(31 downto 0));
  end component;

  component gf_xor_5x
    port (
      input_wip  : in  std_logic_vector(31 downto 0);
      input_fcs  : in  std_logic_vector(31 downto 0);
      output_wip : out  std_logic_vector(31 downto 0));
  end component;

  component gf_xor_6x
    port (
      input_wip  : in  std_logic_vector(31 downto 0);
      input_fcs  : in  std_logic_vector(31 downto 0);
      output_wip : out  std_logic_vector(31 downto 0));
  end component;