crc_top.vhd

一个verilog实现的crc校验

end GF5_xor_2;

architecture GF6_1 of CRC_top is

begin  -- GF6_1

  port map (
    reset                         => reset,
    phi1                          => phi1,
    input_gf6_1 (63 downto 32)    => output_gf5_2 (63 downto 32),
    input_gf6_1 (31 downto 0)     => output_gf5x_2,
    output_gf6_1 (63 downto 32)   => input_gf7_2 (63 downto 32),
    output_gf6_1 (31 downto 0)    => input_gf6x_1);

  if reset='0' then output_gf6_1 <= X'0000000000000000'
     elsif phi1='1' and phi1'event then output_gf6_1 <= input_gf6_1;
  end if;

end GF6_1;


architecture GF6_xor_1 of CRC_top is

begin  -- GF5_xor_1

  port map (
    input_gf6x_1  => output_gf6_1 (31 downto 0),
    output_gf6x_1 => input_gf7_2 (31 downto 0));

  -- Some area optimizations could be done, since we don't use all
  -- the 32 bits of the fcs
  
  output_gf6x_1 (31 => input_gf6x_1(31),
                 30 => input_gf6x_1(30),
                 29 => input_gf6x_1(29),
                 28 => input_gf6x_1(28),
                 27 => (input_gf6x_1(27) xor output_gf6_1(13+32)),
                 26 => (input_gf6x_1(26) xor output_gf6_1(11+32)),
                 25 => (input_gf6x_1(25) xor output_gf6_1(10+32)),
                 24 => (input_gf6x_1(24) xor output_gf6_1(10+32)),
                 23 => (input_gf6x_1(23) xor output_gf6_1(11+32)),
                 22 => (input_gf6x_1(22) xor output_gf6_1(10+32)),
                 21 => (input_gf6x_1(21) xor output_gf6_1(12+32)),
                 20 => (input_gf6x_1(20) xor output_gf6_1(14+32)),
                 19 => (input_gf6x_1(19) xor output_gf6_1(13+32)),
                 18 => (input_gf6x_1(18) xor output_gf6_1(12+32)),
                 17 => (input_gf6x_1(17) xor output_gf6_1(12+32)),
                 16 => (input_gf6x_1(16) xor output_gf6_1(12+32)),
                 15 => (input_gf6x_1(15) xor output_gf6_1(31+32)),
                 14 => (input_gf6x_1(14) xor output_gf6_1(30+32)),
                 13 => (input_gf6x_1(13) xor output_gf6_1(29+32)),
                 12 => (input_gf6x_1(12) xor output_gf6_1(28+32)),
                 11 => (input_gf6x_1(11) xor output_gf6_1(27+32)),
                 10 => (input_gf6x_1(10) xor output_gf6_1(26+32)),
                 9 => (input_gf6x_1(9) xor '0'),
                 8 => (input_gf6x_1(8) xor output_gf6_1(24+32)),
                 7 => (input_gf6x_1(7) xor '0'),
                 6 => (input_gf6x_1(6) xor '0'),
                 5 => (input_gf6x_1(5) xor output_gf6_1(15+32)),
                 4 => (input_gf6x_1(4) xor output_gf6_1(20+32)),
                 3 => (input_gf6x_1(3) xor '0'),
                 2 => (input_gf6x_1(2) xor '0'),
                 1 => (input_gf6x_1(1) xor '0'),
                 0 => (input_gf6x_1(0) xor '0'));
                 

end GF6_xor_1;

architecture GF7_2 of CRC_top is

begin  -- GF7_2

  port map (
    reset                         => reset,
    phi2                          => phi2,
    input_gf7_2 (63 downto 32)    => output_gf6_1 (63 downto 32),
    input_gf7_2 (31 downto 0)     => output_gf6x_1,
    output_gf7_2 (63 downto 32)   => input_gf8_1 (63 downto 32),
    output_gf7_2 (31 downto 0)    => input_gf7x_2);

  if reset='0' then output_gf7_2 <= X'0000000000000000'
     elsif phi2='1' and phi2'event then output_gf7_2 <= input_gf7_2;
  end if;

end GF7_2;


architecture GF7_xor_2 of CRC_top is

begin  -- GF7_xor_2

  port map (
    input_gf7x_2  => output_gf7_2 (31 downto 0),
    output_gf7x_2 => input_gf8_1 (31 downto 0));

  -- Some area optimizations could be done, since we don't use all
  -- the 32 bits of the fcs
  
  output_gf7x_2 (31 => input_gf7x_2(31),
                 30 => input_gf7x_2(30),
                 29 => input_gf7x_2(29),
                 28 => input_gf7x_2(28),
                 27 => (input_gf7x_2(27) xor output_gf7_2(15+32)),
                 26 => (input_gf7x_2(26) xor output_gf7_2(12+32)),
                 25 => (input_gf7x_2(25) xor output_gf7_2(11+32)),
                 24 => (input_gf7x_2(24) xor output_gf7_2(12+32)),
                 23 => (input_gf7x_2(23) xor output_gf7_2(12+32)),
                 22 => (input_gf7x_2(22) xor output_gf7_2(11+32)),
                 21 => (input_gf7x_2(21) xor output_gf7_2(13+32)),
                 20 => (input_gf7x_2(20) xor output_gf7_2(15+32)),
                 19 => (input_gf7x_2(19) xor output_gf7_2(14+32)),
                 18 => (input_gf7x_2(18) xor output_gf7_2(13+32)),
                 17 => (input_gf7x_2(17) xor output_gf7_2(13+32)),
                 16 => (input_gf7x_2(16) xor '0'),
                 15 => (input_gf7x_2(15) xor '0'),
                 14 => (input_gf7x_2(14) xor '0'),
                 13 => (input_gf7x_2(13) xor '0'),
                 12 => (input_gf7x_2(12) xor '0'),
                 11 => (input_gf7x_2(11) xor '0'),
                 10 => (input_gf7x_2(10) xor '0'),
                 9 => input_gf7x_2(9),
                 8 => (input_gf7x_2(8) xor '0'),
                 7 => input_gf7x_2(7),
                 6 => input_gf7x_2(6),
                 5 => (input_gf7x_2(5) xor '0'),
                 4 => (input_gf7x_2(4) xor '0'),
                 3 => input_gf7x_2(3),
                 2 => input_gf7x_2(2),
                 1 => input_gf7x_2(1),
                 0 => input_gf7x_2(0));
                 

end GF7_xor_2;

architecture GF8_1 of CRC_top is

begin  -- GF8_1

  port map (
    reset                         => reset,
    phi1                          => phi1,
    input_gf8_1 (63 downto 32)    => output_gf7_2 (63 downto 32),
    input_gf8_1 (31 downto 0)     => output_gf7x_2,
    output_gf8_1 (63 downto 32)   => input_gf9_2 (63 downto 32),
    output_gf8_1 (31 downto 0)    => input_gf8x_1);

  if reset='0' then output_gf8_1 <= X'0000000000000000'
     elsif phi1='1' and phi1'event then output_gf8_1 <= input_gf8_1;
  end if;

end GF8_1;


architecture GF8_xor_1 of CRC_top is

begin  -- GF8_xor_1

  port map (
    input_gf8x_1  => output_gf8_1 (31 downto 0),
    output_gf8x_1 => input_gf9_2 (31 downto 0));

  -- Some area optimizations could be done, since we don't use all
  -- the 32 bits of the fcs
  
  output_gf8x_1 (31 => input_gf8x_1(31),
                 30 => input_gf8x_1(30),
                 29 => input_gf8x_1(29),
                 28 => input_gf8x_1(28),
                 27 => input_gf8x_1(27),
                 26 => (input_gf8x_1(26) xor output_gf8_1(14+32)),
                 25 => (input_gf8x_1(25) xor output_gf8_1(13+32)),
                 24 => (input_gf8x_1(24) xor output_gf8_1(13+32)),
                 23 => (input_gf8x_1(23) xor output_gf8_1(14+32)),
                 22 => (input_gf8x_1(22) xor output_gf8_1(13+32)),
                 21 => (input_gf8x_1(21) xor output_gf8_1(15+32)),
                 20 => input_gf8x_1(20),
                 19 => (input_gf8x_1(19) xor output_gf8_1(15+32)),
                 18 => (input_gf8x_1(18) xor output_gf8_1(14+32)),
                 17 => (input_gf8x_1(17) xor '0'),
                 16 => input_gf8x_1(16),
                 15 => input_gf8x_1(15),
                 14 => input_gf8x_1(14),
                 13 => input_gf8x_1(13),
                 12 => input_gf8x_1(12),
                 11 => input_gf8x_1(11),
                 10 => input_gf8x_1(10),
                 9 => input_gf8x_1(9),
                 8 => input_gf8x_1(8),
                 7 => input_gf8x_1(7),
                 6 => input_gf8x_1(6),
                 5 => input_gf8x_1(5),
                 4 => input_gf8x_1(4),
                 3 => input_gf8x_1(3),
                 2 => input_gf8x_1(2),
                 1 => input_gf8x_1(1),
                 0 => input_gf8x_1(0));
                 

end GF8_xor_1;

architecture GF9_2 of CRC_top is

begin  -- GF9_2

  port map (
    reset                         => reset,
    phi2                          => phi2,
    input_gf9_2 (63 downto 32)    => output_gf8_1 (63 downto 32),
    input_gf9_2 (31 downto 0)     => output_gf8x_1,
    output_gf9_2 (63 downto 32)   => input_gf10_1 (63 downto 32),
    output_gf9_2 (31 downto 0)    => input_gf9x_2);

  if reset='0' then output_gf9_2 <= X'0000000000000000'
     elsif phi2='1' and phi2'event then output_gf9_2 <= input_gf9_2;
  end if;

end GF9_2;


architecture GF9_xor_2 of CRC_top is

begin  -- GF9_xor_2

  port map (
    input_gf9x_2  => output_gf9_2 (31 downto 0),
    output_gf9x_2 => input_gf10_1 (31 downto 0));

  -- Some area optimizations could be done, since we don't use all
  -- the 32 bits of the fcs
  
  output_gf9x_2 (31 => input_gf9x_2(31),
                 30 => input_gf9x_2(30),
                 29 => input_gf9x_2(29),
                 28 => input_gf9x_2(28),
                 27 => input_gf9x_2(27),
                 26 => (input_gf9x_2(26) xor output_gf9_2(15+32)),
                 25 => (input_gf9x_2(25) xor output_gf9_2(14+32)),
                 24 => (input_gf9x_2(24) xor output_gf9_2(15+32)),
                 23 => (input_gf9x_2(23) xor output_gf9_2(15+32)),
                 22 => (input_gf9x_2(22) xor output_gf9_2(14+32)),
                 21 => (input_gf9x_2(21) xor '0'),
                 20 => input_gf9x_2(20),
                 19 => (input_gf9x_2(19) xor '0'),
                 18 => (input_gf9x_2(18) xor '0'),
                 17 => (input_gf9x_2(17) xor '0'),
                 16 => input_gf9x_2(16),
                 15 => input_gf9x_2(15),
                 14 => input_gf9x_2(14),
                 13 => input_gf9x_2(13),
                 12 => input_gf9x_2(12),
                 11 => input_gf9x_2(11),
                 10 => input_gf9x_2(10),
                 9 => input_gf9x_2(9),
                 8 => input_gf9x_2(8),
                 7 => input_gf9x_2(7),
                 6 => input_gf9x_2(6),
                 5 => input_gf9x_2(5),
                 4 => input_gf9x_2(4),
                 3 => input_gf9x_2(3),
                 2 => input_gf9x_2(2),
                 1 => input_gf9x_2(1),
                 0 => input_gf9x_2(0));
                 

end GF9_xor_2;

architecture GF10_1 of CRC_top is

begin  -- GF10_1

  port map (
    reset                          => reset,
    phi1                           => phi1,
    input_gf10_1 (63 downto 32)    => output_gf9_2 (63 downto 32),
    input_gf10_1 (31 downto 0)     => output_gf9x_2,
    output_gf10_1 (63 downto 32)   => input_gf11_2 (63 downto 32),
    output_gf10_1 (31 downto 0)    => input_gf10x_1);

  if reset='0' then output_gf10_1 <= X'0000000000000000'
     elsif phi1='1' and phi1'event then output_gf10_1 <= input_gf10_1;
  end if;

end GF10_1;


architecture GF10_xor_1 of CRC_top is

begin  -- GF10_xor_1

  port map (
    input_gf10x_1  => output_gf10_1 (31 downto 0),
    output_gf10x_1 => input_gf11_2 (31 downto 0));

  -- Some area optimizations could be done, since we don't use all
  -- the 32 bits of the fcs
  
  output_gf10x_1 (31 => input_gf10x_1(31),
                 30 => input_gf10x_1(30),
                 29 => input_gf10x_1(29),
                 28 => input_gf10x_1(28),
                 27 => input_gf10x_1(27),
                 26 => input_gf10x_1(26),
                 25 => input_gf10x_1(25),
                 24 => (input_gf10x_1(24) xor '0'),
                 23 => (input_gf10x_1(23) xor '0'),
                 22 => (input_gf10x_1(22) xor '0'),
                 21 => input_gf10x_1(21),
                 20 => input_gf10x_1(20),
                 19 => input_gf10x_1(19),
                 18 => input_gf10x_1(18),
                 17 => input_gf10x_1(17),
                 16 => input_gf10x_1(16),
                 15 => input_gf10x_1(15),
                 14 => input_gf10x_1(14),
                 13 => input_gf10x_1(13),
                 12 => input_gf10x_1(12),
                 11 => input_gf10x_1(11),
                 10 => input_gf10x_1(10),
                 9 => input_gf10x_1(9),
                 8 => input_gf10x_1(8),
                 7 => input_gf10x_1(7),
                 6 => input_gf10x_1(6),
                 5 => input_gf10x_1(5),
                 4 => input_gf10x_1(4),
                 3 => input_gf10x_1(3),
                 2 => input_gf10x_1(2),
                 1 => input_gf10x_1(1),
                 0 => input_gf10x_1(0));
                 

end GF10_xor_1;

architecture GF11_2 of CRC_top is

begin  -- GF11_2

  port map (
    reset         => reset,
    phi2          => phi2,
    input_gf11_2  => output_gf10x_1,
    output_gf11_2 => input_gf12_1;

  if reset='0' then output_gf11_2 <= X'0000000000000000'
     elsif phi2='1' and phi2'event then output_gf11_2 <= input_gf11_2;
  end if;

end GF11_2;


architecture GF12_1 of CRC_top is

begin  -- GF12_1

  port map (
    reset         => reset,
    phi1          => phi1,
    input_gf12_1  => output_gf11_2,
    output_gf12_1(15 downto 0) => input_bigx12_1,
    output_gf12_1(31 downto 16) => input_fcs13_2(31 downto 16);

  if reset='0' then output_gf12_1 <= X'0000000000000000'
     elsif phi1='1' and phi1'event then output_gf12_1 <= input_gf12_1;
  end if;

end GF12_1;

-- Final part of the circuit: XOR and output

architecture Big_XOR_12_1 of CRC_top is

begin  -- Big_XOR_12_1

  port map (
    input_bigx12_1  => input_bigx12_1,
    output_bigx12_1 => input_fcs13_2(15 downto 0));

  output_bigx12_1 (15 => (input_bigx12_1(15) xor output12_1(15)),
                   14 => (input_bigx12_1(14) xor output12_1(14)),
                   13 => (input_bigx12_1(13) xor output12_1(13)),
                   12 => (input_bigx12_1(12) xor output12_1(12)),
                   11 => (input_bigx12_1(11) xor output12_1(11)),
                   10 => (input_bigx12_1(10) xor output12_1(10)),
                    9 => (input_bigx12_1(9) xor output12_1(9)),
                    8 => (input_bigx12_1(8) xor output12_1(8)),
                    7 => (input_bigx12_1(7) xor output12_1(7)),
                    6 => (input_bigx12_1(6) xor output12_1(6)),
                    5 => (input_bigx12_1(5) xor output12_1(5)),
                    4 => (input_bigx12_1(4) xor output12_1(4)),
                    3 => (input_bigx12_1(3) xor output12_1(3)),
                    2 => (input_bigx12_1(2) xor output12_1(2)),
                    1 => (input_bigx12_1(1) xor output12_1(1)),
                    0 => (input_bigx12_1(0) xor output12_1(0)));

end Big_XOR_12_1;

architecture FCS_out_13_2 of CRC_top is

begin  -- FCS_out_13_2

  port map (
    reset                       => reset,
    phi2                        => phi2,
    input_fcs13_2(15 downto 0)  => output_bigx12_1,
    input_fcs13_2(31 downto 16) => output_gf12_1,
    output_fcs13_2              => input_gf1x_2, output_fcs13_2);

end FCS_out_13_2;