crc_top.vhd

一个verilog实现的crc校验

  port map (
    reset     => reset,
    phi2      => phi2,
    input7_2  => output6_1,
    output7_2 => input8_1);

  if reset='0' then output7_2 <= X'00000000'
     elsif phi2='1' and phi2'event then output7_2 <= input7_2;
  end if;
                    
end Input7_2;


architecture Input8_1 of CRC_top is

begin  -- Input8_1

  port map (
    reset     => reset,
    phi1      => phi1,
    input8_1  => output7_2,
    output8_1 => input9_2);

  if reset='0' then output8_1 <= X'00000000'
     elsif phi1='1' and phi1'event then output8_1 <= input8_1;
  end if;
                    
end Input8_1;


architecture Input9_2 of CRC_top is

begin  -- Input9_2

  port map (
    reset     => reset,
    phi2      => phi2,
    input9_2  => output8_1,
    output9_2 => input10_1);

  if reset='0' then output9_2 <= X'00000000'
     elsif phi2='1' and phi2'event then output9_2 <= input9_2;
  end if;
                    
end Input9_2;


architecture Input10_1 of CRC_top is

begin  -- Input10_1

  port map (
    reset     => reset,
    phi1      => phi1,
    input10_1  => output9_2,
    output10_1 => input11_2);

  if reset='0' then output10_1 <= X'00000000'
     elsif phi1='1' and phi1'event then output10_1 <= input10_1;
  end if;
                    
end Input10_1;


architecture Input11_2 of CRC_top is

begin  -- Input11_2

  port map (
    reset     => reset,
    phi2      => phi2,
    input11_2  => output10_1,
    output11_2 => input12_1);

  if reset='0' then output11_2 <= X'00000000'
     elsif phi2='1' and phi2'event then output11_2 <= input11_2;
  end if;
                    
end Input11_2;


architecture Input12_1 of CRC_top is

begin  -- Input12_1

  port map (
    reset     => reset,
    phi1      => phi1,
    input12_1  => output11_2,
    output12_1 => input_bigx_1);        -- Big "final" XOR

  if reset='0' then output12_1 <= X'00000000'
     elsif phi1='1' and phi1'event then output12_1 <= input12_1;
  end if;
                    
end Input2_1;

-- Galois Field multiplier

architecture GF1_xor_2 of CRC_top is

begin  -- GF1_xor_2

  port map (
    input_gf1x_2  => fcs_out13_2,
    output_gf1x_2 => input_gf2_1 (31 downto 0));

  -- Some area optimizations could be done, since we don't use all
  -- the 32 bits of the fcs
  
  output_gf1x_2 (31 => (input_gf1x_2(9) xor input_gf1x_2(15)),
                 30 => (input_gf1x_2(8) xor input_gf1x_2(9)),
                 29 => (input_gf1x_2(7) xor input_gf1x_2(8)),
                 28 => (input_gf1x_2(6) xor input_gf1x_2(7)),
                 27 => (input_gf1x_2(5) xor input_gf1x_2(6)),
                 26 => (input_gf1x_2(4) xor input_gf1x_2(5)),
                 25 => (input_gf1x_2(3) xor input_gf1x_2(4)),
                 24 => (input_gf1x_2(2) xor input_gf1x_2(3)),
                 23 => (input_gf1x_2(1) xor input_gf1x_2(1)),
                 22 => (input_gf1x_2(0) xor input_gf1x_2(1)),
                 21 => (input_gf1x_2(0) xor input_gf1x_2(1)),
                 20 => (input_gf1x_2(0) xor input_gf1x_2(2)),
                 19 => (input_gf1x_2(1) xor input_gf1x_2(2)),
                 18 => (input_gf1x_2(0) xor input_gf1x_2(1)),
                 17 => (input_gf1x_2(0) xor input_gf1x_2(1)),
                 16 => (input_gf1x_2(0) xor input_gf1x_2(6)),
                 15 => (input_gf1x_2(5) xor input_gf1x_2(6)),
                 14 => (input_gf1x_2(4) xor input_gf1x_2(5)),
                 13 => (input_gf1x_2(3) xor input_gf1x_2(4)),
                 12 => (input_gf1x_2(2) xor input_gf1x_2(3)),
                 11 => (input_gf1x_2(1) xor input_gf1x_2(2)),
                 10 => (input_gf1x_2(0) xor input_gf1x_2(1)),
                 9 => (input_gf1x_2(0) xor input_gf1x_2(1)),
                 8 => (input_gf1x_2(0) xor input_gf1x_2(3)),
                 7 => (input_gf1x_2(2) xor input_gf1x_2(3)),
                 6 => (input_gf1x_2(1) xor input_gf1x_2(2)),
                 5 => (input_gf1x_2(0) xor input_gf1x_2(1)),
                 4 => (input_gf1x_2(0) xor input_gf1x_2(5)),
                 3 => (input_gf1x_2(4) xor input_gf1x_2(7)),
                 2 => (input_gf1x_2(3) xor input_gf1x_2(6)),
                 1 => (input_gf1x_2(2) xor input_gf1x_2(5)),
                 0 => (input_gf1x_2(1) xor input_gf1x_2(4)));
                 

end GF1_xor_2;

architecture GF2_1 of CRC_top is

begin  -- GF2_1

  port map (
    reset                         => reset,
    phi1                          => phi1,
    input_gf2_1 (63 downto 32)    => fcs_13_2,
    input_gf2_1 (31 downto 0)     => output_gf1x_2,
    output_gf2_1 (63 downto 32)   => input_gf3_2,
    output_gf2_1 (31 downto 0)    => input_gf2x_1);

  if reset='0' then output_gf2_1 <= X'0000000000000000'
     elsif phi1='1' and phi1'event then output_gf2_1 <= input_gf2_1;
  end if;

end GF2_1;


architecture GF2_xor_1 of CRC_top is

begin  -- GF2_xor_1

  port map (
    input_gf2x_1  => output_gf2_1 (31 downto 0),
    output_gf2x_1 => input_gf3_2 (31 downto 0));

  -- Some area optimizations could be done, since we don't use all
  -- the 32 bits of the fcs
  
  output_gf2x_1 (31 => input_gf2x_1(31),
                 30 => (input_gf2x_1(30) xor output_gf2_1(14+32)),
                 29 => (input_gf2x_1(29) xor output_gf2_1(9+32)),
                 28 => (input_gf2x_1(28) xor output_gf2_1(8+32)),
                 27 => (input_gf2x_1(27) xor output_gf2_1(7+32)),
                 26 => (input_gf2x_1(26) xor output_gf2_1(6+32)),
                 25 => (input_gf2x_1(25) xor output_gf2_1(5+32)),
                 24 => (input_gf2x_1(24) xor output_gf2_1(4+32)),
                 23 => (input_gf2x_1(23) xor output_gf2_1(3+32)),
                 22 => (input_gf2x_1(22) xor output_gf2_1(2+32)),
                 21 => (input_gf2x_1(21) xor output_gf2_1(3+32)),
                 20 => (input_gf2x_1(20) xor output_gf2_1(3+32)),
                 19 => (input_gf2x_1(19) xor output_gf2_1(3+32)),
                 18 => (input_gf2x_1(18) xor output_gf2_1(2+32)),
                 17 => (input_gf2x_1(17) xor output_gf2_1(7+32)),
                 16 => (input_gf2x_1(16) xor output_gf2_1(7+32)),
                 15 => (input_gf2x_1(15) xor output_gf2_1(7+32)),
                 14 => (input_gf2x_1(14) xor output_gf2_1(6+32)),
                 13 => (input_gf2x_1(13) xor output_gf2_1(5+32)),
                 12 => (input_gf2x_1(12) xor output_gf2_1(4+32)),
                 11 => (input_gf2x_1(11) xor output_gf2_1(3+32)),
                 10 => (input_gf2x_1(10) xor output_gf2_1(2+32)),
                 9 => (input_gf2x_1(9) xor output_gf2_1(4+32)),
                 8 => (input_gf2x_1(8) xor output_gf2_1(4+32)),
                 7 => (input_gf2x_1(7) xor output_gf2_1(8+32)),
                 6 => (input_gf2x_1(6) xor output_gf2_1(7+32)),
                 5 => (input_gf2x_1(5) xor output_gf2_1(6+32)),
                 4 => (input_gf2x_1(4) xor output_gf2_1(8+32)),
                 3 => (input_gf2x_1(3) xor output_gf2_1(9+32)),
                 2 => (input_gf2x_1(2) xor output_gf2_1(8+32)),
                 1 => (input_gf2x_1(1) xor output_gf2_1(7+32)),
                 0 => (input_gf2x_1(0) xor output_gf2_1(6+32)));
                 

end GF2_xor_1;

architecture GF3_2 of CRC_top is

begin  -- GF3_2

  port map (
    reset                         => reset,
    phi2                          => phi2,
    input_gf3_2 (63 downto 32)    => output_gf2_1 (63 downto 32),
    input_gf3_2 (31 downto 0)     => output_gf2x_1,
    output_gf3_2 (63 downto 32)   => input_gf4_1,
    output_gf3_2 (31 downto 0)    => input_gf3x_2);

  if reset='0' then output_gf3_2 <= X'0000000000000000'
     elsif phi2='1' and phi2'event then output_gf3_2 <= input_gf3_2;
  end if;

end GF3_2;


architecture GF3_xor_2 of CRC_top is

begin  -- GF3_xor_2

  port map (
    input_gf3x_2  => output_gf3_2 (31 downto 0),
    output_gf3x_2 => input_gf4_1 (31 downto 0));

  -- Some area optimizations could be done, since we don't use all
  -- the 32 bits of the fcs
  
  output_gf3x_2 (31 => input_gf3x_1(31),
                 30 => (input_gf3x_1(30) xor output_gf3_2(15+32)),
                 29 => (input_gf3x_1(29) xor output_gf3_2(13+32)),
                 28 => (input_gf3x_1(28) xor output_gf3_2(12+32)),
                 27 => (input_gf3x_1(27) xor output_gf3_2(9+32)),
                 26 => (input_gf3x_1(26) xor output_gf3_2(8+32)),
                 25 => (input_gf3x_1(25) xor output_gf3_2(7+32)),
                 24 => (input_gf3x_1(24) xor output_gf3_2(6+32)),
                 23 => (input_gf3x_1(23) xor output_gf3_2(5+32)),
                 22 => (input_gf3x_1(22) xor output_gf3_2(4+32)),
                 21 => (input_gf3x_1(21) xor output_gf3_2(4+32)),
                 20 => (input_gf3x_1(20) xor output_gf3_2(4+32)),
                 19 => (input_gf3x_1(19) xor output_gf3_2(9+32)),
                 18 => (input_gf3x_1(18) xor output_gf3_2(8+32)),
                 17 => (input_gf3x_1(17) xor output_gf3_2(8+32)),
                 16 => (input_gf3x_1(16) xor output_gf3_2(8+32)),
                 15 => (input_gf3x_1(15) xor output_gf3_2(10+32)),
                 14 => (input_gf3x_1(14) xor output_gf3_2(9+32)),
                 13 => (input_gf3x_1(13) xor output_gf3_2(8+32)),
                 12 => (input_gf3x_1(12) xor output_gf3_2(7+32)),
                 11 => (input_gf3x_1(11) xor output_gf3_2(6+32)),
                 10 => (input_gf3x_1(10) xor output_gf3_2(5+32)),
                 9 => (input_gf3x_1(9) xor output_gf3_2(5+32)),
                 8 => (input_gf3x_1(8) xor output_gf3_2(9+32)),
                 7 => (input_gf3x_1(7) xor output_gf3_2(13+32)),
                 6 => (input_gf3x_1(6) xor output_gf3_2(12+32)),
                 5 => (input_gf3x_1(5) xor output_gf3_2(9+32)),
                 4 => (input_gf3x_1(4) xor output_gf3_2(10+32)),
                 3 => (input_gf3x_1(3) xor output_gf3_2(10+32)),
                 2 => (input_gf3x_1(2) xor output_gf3_2(9+32)),
                 1 => (input_gf3x_1(1) xor output_gf3_2(8+32)),
                 0 => (input_gf3x_1(0) xor output_gf3_2(7+32)));
                 

end GF3_xor_2;

architecture GF4_1 of CRC_top is

begin  -- GF4_1

  port map (
    reset                         => reset,
    phi1                          => phi1,
    input_gf4_1 (63 downto 32)    => output_gf3_2 (63 downto 32),
    input_gf4_1 (31 downto 0)     => output_gf3x_2,
    output_gf4_1 (63 downto 32)   => input_gf5_2,
    output_gf4_1 (31 downto 0)    => input_gf4x_1);

  if reset='0' then output_gf4_1 <= X'0000000000000000'
     elsif phi1='1' and phi1'event then output_gf4_1 <= input_gf4_1;
  end if;

end GF4_1;


architecture GF4_xor_1 of CRC_top is

begin  -- GF4_xor_1

  port map (
    input_gf4x_1  => output_gf4_1 (31 downto 0),
    output_gf4x_1 => input_gf5_2 (31 downto 0));

  -- Some area optimizations could be done, since we don't use all
  -- the 32 bits of the fcs
  
  output_gfx4_1 (31 => input_gf4x_1(31),
                 30 => input_gf4x_1(30),
                 29 => (input_gf4x_1(29) xor output_gf4_1(14+32)),
                 28 => (input_gf4x_1(28) xor output_gf4_1(13+32)),
                 27 => (input_gf4x_1(27) xor output_gf4_1(11+32)),
                 26 => (input_gf4x_1(26) xor output_gf4_1(9+32)),
                 25 => (input_gf4x_1(25) xor output_gf4_1(8+32)),
                 24 => (input_gf4x_1(24) xor output_gf4_1(7+32)),
                 23 => (input_gf4x_1(23) xor output_gf4_1(6+32)),
                 22 => (input_gf4x_1(22) xor output_gf4_1(5+32)),
                 21 => (input_gf4x_1(21) xor output_gf4_1(5+32)),
                 20 => (input_gf4x_1(20) xor output_gf4_1(11+32)),
                 19 => (input_gf4x_1(19) xor output_gf4_1(10+32)),
                 18 => (input_gf4x_1(18) xor output_gf4_1(9+32)),
                 17 => (input_gf4x_1(17) xor output_gf4_1(9+32)),
                 16 => (input_gf4x_1(16) xor output_gf4_1(10+32)),
                 15 => (input_gf4x_1(15) xor output_gf4_1(11+32)),
                 14 => (input_gf4x_1(14) xor output_gf4_1(10+32)),
                 13 => (input_gf4x_1(13) xor output_gf4_1(9+32)),
                 12 => (input_gf4x_1(12) xor output_gf4_1(8+32)),
                 11 => (input_gf4x_1(11) xor output_gf4_1(7+32)),
                 10 => (input_gf4x_1(10) xor output_gf4_1(6+32)),
                 9 => (input_gf4x_1(9) xor output_gf4_1(15+32)),
                 8 => (input_gf4x_1(8) xor output_gf4_1(14+32)),
                 7 => (input_gf4x_1(7) xor output_gf4_1(14+32)),
                 6 => (input_gf4x_1(6) xor output_gf4_1(13+32)),
                 5 => (input_gf4x_1(5) xor output_gf4_1(11+32)),
                 4 => (input_gf4x_1(4) xor output_gf4_1(11+32)),
                 3 => (input_gf4x_1(3) xor output_gf4_1(13+32)),
                 2 => (input_gf4x_1(2) xor output_gf4_1(12+32)),
                 1 => (input_gf4x_1(1) xor output_gf4_1(11+32)),
                 0 => (input_gf4x_1(0) xor output_gf4_1(10+32)));
                 

end GF4_xor_1;

architecture GF5_2 of CRC_top is

begin  -- GF5_2

  port map (
    reset                         => reset,
    phi2                          => phi2,
    input_gf5_2 (63 downto 32)    => output_gf4_1 (63 downto 32),
    input_gf5_2 (31 downto 0)     => output_gf4x_1,
    output_gf5_2 (63 downto 32)   => input_gf6_1 (63 downto 32),
    output_gf5_2 (31 downto 0)    => input_gf5x_2);

  if reset='0' then output_gf5_2 <= X'0000000000000000'
     elsif phi2='1' and phi2'event then output_gf5_2 <= input_gf5_2;
  end if;

end GF5_2;


architecture GF5_xor_2 of CRC_top is

begin  -- GF5_xor_2

  port map (
    input_gf5x_2  => output_gf5_2 (31 downto 0),
    output_gf5x_2 => input_gf6_1 (31 downto 0));

  -- Some area optimizations could be done, since we don't use all
  -- the 32 bits of the fcs
  
  output_gf5x_2 (31 => input_gf5x_2(31),
                 30 => input_gf5x_2(30),
                 29 => (input_gf5x_2(29) xor output_gf5_2(15+32)),
                 28 => (input_gf5x_2(28) xor output_gf5_2(14+32)),
                 27 => (input_gf5x_2(27) xor output_gf5_2(12+32)),
                 26 => (input_gf5x_2(26) xor output_gf5_2(10+32)),
                 25 => (input_gf5x_2(25) xor output_gf5_2(9+32)),
                 24 => (input_gf5x_2(24) xor output_gf5_2(8+32)),
                 23 => (input_gf5x_2(23) xor output_gf5_2(7+32)),
                 22 => (input_gf5x_2(22) xor output_gf5_2(6+32)),
                 21 => (input_gf5x_2(21) xor output_gf5_2(10+32)),
                 20 => (input_gf5x_2(20) xor output_gf5_2(12+32)),
                 19 => (input_gf5x_2(19) xor output_gf5_2(11+32)),
                 18 => (input_gf5x_2(18) xor output_gf5_2(10+32)),
                 17 => (input_gf5x_2(17) xor output_gf5_2(11+32)),
                 16 => (input_gf5x_2(16) xor output_gf5_2(11+32)),
                 15 => (input_gf5x_2(15) xor output_gf5_2(15+32)),
                 14 => (input_gf5x_2(14) xor output_gf5_2(14+32)),
                 13 => (input_gf5x_2(13) xor output_gf5_2(13+32)),
                 12 => (input_gf5x_2(12) xor output_gf5_2(12+32)),
                 11 => (input_gf5x_2(11) xor output_gf5_2(11+32)),
                 10 => (input_gf5x_2(10) xor output_gf5_2(10+32)),
                 9 => (input_gf5x_2(9) xor output_gf5_2(25+32)),
                 8 => (input_gf5x_2(8) xor output_gf5_2(15+32)),
                 7 => (input_gf5x_2(7) xor output_gf5_2(23+32)),
                 6 => (input_gf5x_2(6) xor output_gf5_2(22+32)),
                 5 => (input_gf5x_2(5) xor output_gf5_2(12+32)),
                 4 => (input_gf5x_2(4) xor output_gf5_2(14+32)),
                 3 => (input_gf5x_2(3) xor output_gf5_2(19+32)),
                 2 => (input_gf5x_2(2) xor output_gf5_2(18+32)),
                 1 => (input_gf5x_2(1) xor output_gf5_2(17+32)),
                 0 => (input_gf5x_2(0) xor output_gf5_2(16+32)));