crc_top.vhd

一个verilog实现的crc校验

library IEEE;
use IEEE.std_logic_1164.all;

entity CRC_top is
  
  port (
    phi1    : in  std_logic;
                                        -- We will use the two phase discipline
                                        -- which we don't generate.
    phi2    : in  std_logic;
    reset   : in  std_logic;            -- #RESET
    input   : in  std_logic_vector(15 downto 0);
                                        -- The serial/parallel conversion has been made somewhere else
    FCS_out : out std_logic_vector(31 downto 0));

end CRC_top;

architecture structural of CRC_top is

begin  -- Structural description of the CRC
       -- We will describe all the pipelining steps

  -- These first pipelining steps are the "waiting" steps. The data will flow
  -- through the registers.

  -- The nomenclature can be explained in the following way:
  -- Input<stage no.>_<clock phase>  => Registers in the "wait" region

  -- For the Galois Field multiplier:
  -- GF<stage no.>_<clock phase>     => Registers of the GF multiplier
  -- GF<stage no.>_xor_<clock phase> => Combinational logic of the GF mult.
  
  component Input1_2
  port (
      reset     : in  std_logic;
      phi2      : in  std_logic;
      input1_2  : in  std_logic_vector (15 downto 0);   -- Directly from the serial/parallel register
      output1_2 : out std_logic_vector (15 downto 0));  -- To the next step
  end component;

  component Input2_1
    port (
      reset     : in  std_logic;
      phi1      : in  std_logic;
      input2_1  : in  std_logic_vector (15 downto 0);
      output2_1 : out std_logic_vector (15 downto 0));
  end component;

  component Input3_2
    port (
      reset     : in  std_logic;
      phi2      : in  std_logic;
      input3_2  : in  std_logic_vector (15 downto 0);   
      output3_2 : out std_logic_vector (15 downto 0));
  end component;

  component Input4_1
    port (
      reset     : in  std_logic;
      phi1      : in  std_logic;
      input4_1  : in  std_logic_vector (15 downto 0);
      output4_1 : out std_logic_vector (15 downto 0));
  end component;

  component Input5_2
    port (
      reset     : in  std_logic;
      phi2      : in  std_logic;
      input5_2  : in  std_logic_vector (15 downto 0);   
      output5_2 : out std_logic_vector (15 downto 0));
  end component;

  component Input6_1
    port (
      reset     : in  std_logic;
      phi1      : in  std_logic;
      input6_1  : in  std_logic_vector (15 downto 0);
      output6_1 : out std_logic_vector (15 downto 0));
  end component;

  component Input7_2
    port (
      reset     : in  std_logic;
      phi2      : in  std_logic;
      input7_2  : in  std_logic_vector (15 downto 0);   
      output7_2 : out std_logic_vector (15 downto 0));
  end component;

  component Input8_1
    port (
      reset     : in  std_logic;
      phi1      : in  std_logic;
      input8_1  : in  std_logic_vector (15 downto 0);
      output8_1 : out std_logic_vector (15 downto 0));
  end component;

  component Input9_2
    port (
      reset     : in  std_logic;
      phi2      : in  std_logic;
      input9_2  : in  std_logic_vector (15 downto 0);   
      output9_2 : out std_logic_vector (15 downto 0));
  end component;

  component Input10_1
    port (
      reset      : in  std_logic;
      phi1       : in  std_logic;
      input10_1  : in  std_logic_vector (15 downto 0);
      output10_1 : out std_logic_vector (15 downto 0));
  end component;

  component Input11_2
    port (
      reset      : in  std_logic;
      phi2       : in  std_logic;
      input11_2  : in  std_logic_vector (15 downto 0);   
      output11_2 : out std_logic_vector (15 downto 0));
  end component;

  component Input12_1
    port (
      reset      : in  std_logic;
      phi1       : in  std_logic;
      input12_1  : in  std_logic_vector (15 downto 0);
      output12_1 : out std_logic_vector (15 downto 0));
  end component;

  -- Galois Field pipelining registers and combinational stuff

  component GF1_xor_2
    port (
      input_gf1x_2  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
      output_gf1x_2 : out std_logic_vector (31 downto 0));  -- The new WIP
  end component;

  component GF2_1
    port (
      reset       : in  std_logic;
      phi1        : in  std_logic;
      input_gf2_1  : in  std_logic_vector (63 downto 0);
      output_gf2_1 : out std_logic_vector (63 downto 0));
  end component;

  component GF2_xor_1
    port (
      input_gf2x_1  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
      output_gf2x_1 : out std_logic_vector (31 downto 0));  -- The new WIP
  end component;

  component GF3_2
    port (
      reset       : in  std_logic;
      phi2        : in  std_logic;
      input_gf3_2  : in  std_logic_vector (63 downto 0);
      output_gf3_2 : out std_logic_vector (63 downto 0));
  end component;

  component GF3_xor_2
    port (
      input_gf3x_2  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
      output_gf3x_2 : out std_logic_vector (31 downto 0));  -- The new WIP
  end component;

  component GF4_1
    port (
      reset  : in  std_logic;
      phi1   : in  std_logic;
      input_gf4_1  : in  std_logic_vector (63 downto 0);
      output_gf4_1 : out std_logic_vector (63 downto 0));
  end component;

  component GF4_xor_1
    port (
      input_gf4x_1  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
      output_gf4x_1 : out std_logic_vector (31 downto 0));  -- The new WIP
  end component;

  component GF5_2
    port (
      reset       : in  std_logic;
      phi2        : in  std_logic;
      input_gf5_2  : in  std_logic_vector (63 downto 0);
      output_gf5_2 : out std_logic_vector (63 downto 0));
  end component;

  component GF5_xor_2
    port (
      input_gf5x_2  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
      output_gf5x_2 : out std_logic_vector (31 downto 0));  -- The new WIP
  end component;

  component GF6_1
    port (
      reset       : in  std_logic;
      phi1        : in  std_logic;
      input_gf6_1  : in  std_logic_vector (63 downto 0);
      output_gf6_1 : out std_logic_vector (63 downto 0));
  end component;

  component GF6_xor_1
    port (
      input_gf6x_1  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
      output_gf6x_1 : out std_logic_vector (31 downto 0));  -- The new WIP
  end component;

  component GF7_2
    port (
      reset       : in  std_logic;
      phi2        : in  std_logic;
      input_gf7_2  : in  std_logic_vector (63 downto 0);
      output_gf7_2 : out std_logic_vector (63 downto 0));
  end component;

  component GF7_xor_2
    port (
      input_gf7x_2  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
      output_gf7x_2 : out std_logic_vector (31 downto 0));  -- The new WIP
  end component;

  component GF8_1
    port (
      reset       : in  std_logic;
      phi1        : in  std_logic;
      input_gf8_1  : in  std_logic_vector (63 downto 0);
      output_gf8_1 : out std_logic_vector (63 downto 0));
  end component;

  component GF8_xor_1
    port (
      input_gf8x_1  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
      output_gf8x_1 : out std_logic_vector (31 downto 0));  -- The new WIP
  end component;

  component GF9_2
    port (
      reset       : in  std_logic;
      phi2        : in  std_logic;
      input_gf9_2  : in  std_logic_vector (63 downto 0);
      output_gf9_2 : out std_logic_vector (63 downto 0));
  end component;

  component GF9_xor_2
    port (
      input_gf9x_2  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
      output_gf9x_2 : out std_logic_vector (31 downto 0));  -- The new WIP
  end component;

  component GF10_1
    port (
      reset        : in  std_logic;
      phi1         : in  std_logic;
      input_gf10_1  : in  std_logic_vector (63 downto 0);
      output_gf10_1 : out std_logic_vector (63 downto 0));
  end component;

  component GF10_xor_1
    port (
      input_gf10x_1  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
      output_gf10x_1 : out std_logic_vector (31 downto 0));  -- The new WIP
  end component;

  component GF11_2
    port (
      reset        : in  std_logic;
      phi2         : in  std_logic;
      input_gf11_2  : in  std_logic_vector (63 downto 0);
      output_gf11_2 : out std_logic_vector (63 downto 0));
  end component;

--  component GF11_xor_2
--    port (
--      input_gf11x_2  : in  std_logic_vector (31 downto 0);   -- Inputs = WIP + "Original data"
--      output_gf11x_2 : out std_logic_vector (31 downto 0));  -- The new WIP
--  end component;

  component GF12_1
    port (
      reset         : in  std_logic;
      phi1          : in  std_logic;
      input_gf12_1  : in  std_logic_vector (31 downto 0);
      output_gf12_1 : out std_logic_vector (31 downto 0));
  end component;
  
  -- Big XOR and output register (FCS)

  component Big_XOR12_1
    port (
      input_bigx12_1  : in  std_logic_vector (15 downto 0);
      output_bigx12_1 : out std_logic_vector (15 downto 0));
  end component;

  component FCS_out13_2
    port (
      reset          : in std_logic;
      phi2           : in std_logic;
      input_fcs13_2  : in  std_logic_vector (31 downto 0);
      output_fcs13_2 : out std_logic_vector (31 downto 0));  -- FCS_out and feedback to the GF multiplier
  end component;

end structural;

-- Now it is time to define each component and the way they work

architecture Input1_2 of CRC_top is

begin  -- Input1_2

  port map (
    reset     => reset,
    phi2      => phi2,
    input1_2  => input,
    output1_2 => input2_1);

  if reset='0' then output1_2 <= X'00000000'
     elsif phi2='1' and phi2'event then output1_2 <= input1_2;
  end if;
    
end Input1_2;


architecture Input2_1 of CRC_top is

begin  -- Input2_1

  port map (
    reset     => reset,
    phi1      => phi1,
    input2_1  => output1_2,
    output2_1 => input3_1);

  if reset='0' then output2_1 <= X'00000000'
     elsif phi1='1' and phi1'event then output2_1 <= input2_1;
  end if;
                    
end Input2_1;


architecture Input3_2 of CRC_top is

begin  -- Input3_2

  port map (
    reset     => reset,
    phi2      => phi2,
    input3_2  => output2_1,
    output3_2 => input4_1);

  if reset='0' then output3_2 <= X'00000000'
     elsif phi2='1' and phi2'event then output3_2 <= input3_2;
  end if;
                    
end Input3_2;


architecture Input4_1 of CRC_top is

begin  -- Input4_1

  port map (
    reset     => reset,
    phi1      => phi1,
    input4_1  => output3_2,
    output4_1 => input5_2);

  if reset='0' then output4_1 <= X'00000000'
     elsif phi1='1' and phi1'event then output4_1 <= input4_1;
  end if;
                    
end Input4_1;


architecture Input5_2 of CRC_top is

begin  -- Input5_2

  port map (
    reset     => reset,
    phi2      => phi2,
    input5_2  => output4_1,
    output5_2 => input6_1);

  if reset='0' then output5_2 <= X'00000000'
     elsif phi2='1' and phi2'event then output5_2 <= input5_2;
  end if;
                    
end Input5_2;


architecture Input6_1 of CRC_top is

begin  -- Input6_1

  port map (
    reset     => reset,
    phi1      => phi1,
    input6_1  => output5_2,
    output6_1 => input7_2);

  if reset='0' then output6_1 <= X'00000000'
     elsif phi1='1' and phi1'event then output6_1 <= input6_1;
  end if;
                    
end Input6_1;


architecture Input7_2 of CRC_top is

begin  -- Input7_2