crc_top_syn.v

一个verilog实现的crc校验

    assign input_wip_23 = input_wip[23];
    assign input_wip_22 = input_wip[22];
    assign input_wip_21 = input_wip[21];
    assign input_wip_20 = input_wip[20];
    assign input_wip_19 = input_wip[19];
    assign input_wip_18 = input_wip[18];
    assign input_wip_17 = input_wip[17];
    assign input_wip_16 = input_wip[16];
    assign input_wip_15 = input_wip[15];
    assign input_wip_14 = input_wip[14];
    assign input_wip_13 = input_wip[13];
    assign input_wip_11 = input_wip[11];
    assign input_wip_10 = input_wip[10];
    assign input_wip_9 = input_wip[9];
    assign input_wip_8 = input_wip[8];
    assign input_wip_7 = input_wip[7];
    assign input_wip_6 = input_wip[6];
    assign input_wip_5 = input_wip[5];
    assign input_wip_4 = input_wip[4];
    assign input_wip_3 = input_wip[3];
    assign input_wip_2 = input_wip[2];
    assign input_wip_1 = input_wip[1];
    assign input_wip_0 = input_wip[0];
    assign output_wip[31] = input_wip_31;
    assign output_wip[30] = input_wip_30;
    assign output_wip[29] = input_wip_29;
    assign output_wip[28] = input_wip_28;
    assign output_wip[27] = input_wip_27;
    assign output_wip[26] = input_wip_26;
    assign output_wip[25] = input_wip_25;
    assign output_wip[24] = input_wip_24;
    assign output_wip[23] = input_wip_23;
    assign output_wip[22] = input_wip_22;
    assign output_wip[21] = input_wip_21;
    assign output_wip[20] = input_wip_20;
    assign output_wip[19] = input_wip_19;
    assign output_wip[18] = input_wip_18;
    assign output_wip[17] = input_wip_17;
    assign output_wip[16] = input_wip_16;
    assign output_wip[15] = input_wip_15;
    assign output_wip[14] = input_wip_14;
    assign output_wip[13] = input_wip_13;
    assign output_wip[11] = input_wip_11;
    assign output_wip[10] = input_wip_10;
    assign output_wip[9] = input_wip_9;
    assign output_wip[8] = input_wip_8;
    assign output_wip[7] = input_wip_7;
    assign output_wip[6] = input_wip_6;
    assign output_wip[5] = input_wip_5;
    assign output_wip[4] = input_wip_4;
    assign output_wip[3] = input_wip_3;
    assign output_wip[2] = input_wip_2;
    assign output_wip[1] = input_wip_1;
    assign output_wip[0] = input_wip_0;
    EO1 U7 ( .A(input_wip[12]), .B(input_fcs[16]), .Q(output_wip[12]) );
endmodule


module gf_phi1_register_out ( reset, phi1, input_wip, output_final );
input  [31:0] input_wip;
output [31:0] output_final;
input  reset, phi1;
    wire n107, n108, n110, n112, n114, n116, n118, n120, n122, n124, n126, 
        n128, n130, n132, n134, n136, n138;
    DFA2 output_final_reg_29 ( .C(phi1), .D(input_wip[29]), .Q(output_final
        [29]), .RN(n107) );
    DFA2 output_final_reg_27 ( .C(phi1), .D(input_wip[27]), .Q(output_final
        [27]), .RN(n107) );
    DFA2 output_final_reg_25 ( .C(phi1), .D(input_wip[25]), .Q(output_final
        [25]), .RN(n107) );
    DFA2 output_final_reg_24 ( .C(phi1), .D(input_wip[24]), .Q(output_final
        [24]), .RN(n107) );
    DFA2 output_final_reg_23 ( .C(phi1), .D(input_wip[23]), .Q(output_final
        [23]), .RN(n107) );
    DFA2 output_final_reg_22 ( .C(phi1), .D(input_wip[22]), .Q(output_final
        [22]), .RN(n107) );
    DFA2 output_final_reg_21 ( .C(phi1), .D(input_wip[21]), .Q(output_final
        [21]), .RN(n107) );
    DFA2 output_final_reg_20 ( .C(phi1), .D(input_wip[20]), .Q(output_final
        [20]), .RN(n107) );
    DFA2 output_final_reg_19 ( .C(phi1), .D(input_wip[19]), .Q(output_final
        [19]), .RN(n107) );
    DFA2 output_final_reg_18 ( .C(phi1), .D(input_wip[18]), .Q(output_final
        [18]), .RN(n107) );
    DFA2 output_final_reg_17 ( .C(phi1), .D(input_wip[17]), .Q(output_final
        [17]), .RN(n107) );
    DFA2 output_final_reg_16 ( .C(phi1), .D(input_wip[16]), .Q(output_final
        [16]), .RN(n107) );
    BU8 U80 ( .A(reset), .Q(n107) );
    IN2 U81 ( .A(n108), .Q(output_final[6]) );
    IN2 U82 ( .A(n110), .Q(output_final[10]) );
    IN2 U83 ( .A(n112), .Q(output_final[0]) );
    IN2 U84 ( .A(n114), .Q(output_final[14]) );
    IN2 U85 ( .A(n116), .Q(output_final[13]) );
    IN2 U86 ( .A(n118), .Q(output_final[3]) );
    DFA output_final_reg_3 ( .C(phi1), .D(input_wip[3]), .QN(n118), .RN(n107)
         );
    DFA output_final_reg_13 ( .C(phi1), .D(input_wip[13]), .QN(n116), .RN(n107
        ) );
    DFA output_final_reg_14 ( .C(phi1), .D(input_wip[14]), .QN(n114), .RN(n107
        ) );
    DFA output_final_reg_0 ( .C(phi1), .D(input_wip[0]), .QN(n112), .RN(n107)
         );
    DFA output_final_reg_10 ( .C(phi1), .D(input_wip[10]), .QN(n110), .RN(n107
        ) );
    DFA output_final_reg_6 ( .C(phi1), .D(input_wip[6]), .QN(n108), .RN(n107)
         );
    IN3 U87 ( .A(n120), .Q(output_final[15]) );
    DFA2 output_final_reg_15 ( .C(phi1), .D(input_wip[15]), .QN(n120), .RN(
        n107) );
    IN3 U88 ( .A(n122), .Q(output_final[12]) );
    DFA2 output_final_reg_12 ( .C(phi1), .D(input_wip[12]), .QN(n122), .RN(
        n107) );
    IN3 U89 ( .A(n124), .Q(output_final[4]) );
    DFA2 output_final_reg_4 ( .C(phi1), .D(input_wip[4]), .QN(n124), .RN(n107)
         );
    IN3 U90 ( .A(n126), .Q(output_final[5]) );
    DFA2 output_final_reg_5 ( .C(phi1), .D(input_wip[5]), .QN(n126), .RN(n107)
         );
    IN3 U91 ( .A(n128), .Q(output_final[2]) );
    DFA2 output_final_reg_2 ( .C(phi1), .D(input_wip[2]), .QN(n128), .RN(n107)
         );
    IN3 U92 ( .A(n130), .Q(output_final[9]) );
    DFA2 output_final_reg_9 ( .C(phi1), .D(input_wip[9]), .QN(n130), .RN(n107)
         );
    IN3 U93 ( .A(n132), .Q(output_final[11]) );
    DFA2 output_final_reg_11 ( .C(phi1), .D(input_wip[11]), .QN(n132), .RN(
        n107) );
    IN3 U94 ( .A(n134), .Q(output_final[7]) );
    DFA2 output_final_reg_7 ( .C(phi1), .D(input_wip[7]), .QN(n134), .RN(n107)
         );
    IN3 U95 ( .A(n136), .Q(output_final[1]) );
    DFA2 output_final_reg_1 ( .C(phi1), .D(input_wip[1]), .QN(n136), .RN(n107)
         );
    IN3 U96 ( .A(n138), .Q(output_final[8]) );
    DFA2 output_final_reg_8 ( .C(phi1), .D(input_wip[8]), .QN(n138), .RN(n107)
         );
    DFA2 output_final_reg_26 ( .C(phi1), .D(input_wip[26]), .Q(output_final
        [26]), .RN(n107) );
    DFA2 output_final_reg_30 ( .C(phi1), .D(input_wip[30]), .Q(output_final
        [30]), .RN(n107) );
    DFA2 output_final_reg_31 ( .C(phi1), .D(input_wip[31]), .Q(output_final
        [31]), .RN(n107) );
    DFA2 output_final_reg_28 ( .C(phi1), .D(input_wip[28]), .Q(output_final
        [28]), .RN(n107) );
endmodule


module gf_phi1_register_0 ( reset, phi1, input_wip, input_fcs, output_wip, 
    output_fcs );
output [31:0] output_fcs;
input  [31:0] input_fcs;
input  [31:0] input_wip;
output [31:0] output_wip;
input  reset, phi1;
    wire n187, n188, n189, n191, n193, n195, n197, n199, n201, n203, n205, 
        n207, n209, n211, n213, n215, n217, n219, n221, n223, n225, n227, n229, 
        n231, n233, n235, n237, n239, n241, n243, n245, n247, n249, n251, n253, 
        n255, n257, n259, n261, n263, n265, n267, n269, n271, n273;
    DFA output_wip_reg_27 ( .C(phi1), .D(input_wip[27]), .QN(n203), .RN(n188)
         );
    DFA output_wip_reg_24 ( .C(phi1), .D(input_wip[24]), .QN(n209), .RN(n187)
         );
    DFA output_wip_reg_22 ( .C(phi1), .D(input_wip[22]), .QN(n211), .RN(n187)
         );
    DFA output_wip_reg_23 ( .C(phi1), .D(input_wip[23]), .QN(n227), .RN(n188)
         );
    IN1 U147 ( .A(n197), .Q(output_wip[30]) );
    IN1 U148 ( .A(n199), .Q(output_wip[29]) );
    IN1 U149 ( .A(n203), .Q(output_wip[27]) );
    IN1 U150 ( .A(n207), .Q(output_wip[25]) );
    IN1 U151 ( .A(n209), .Q(output_wip[24]) );
    IN1 U152 ( .A(n211), .Q(output_wip[22]) );
    IN1 U153 ( .A(n213), .Q(output_wip[19]) );
    IN1 U154 ( .A(n215), .Q(output_wip[17]) );
    IN1 U155 ( .A(n217), .Q(output_wip[3]) );
    IN1 U156 ( .A(n219), .Q(output_wip[15]) );
    IN1 U157 ( .A(n221), .Q(output_wip[13]) );
    IN1 U158 ( .A(n223), .Q(output_wip[12]) );
    IN1 U159 ( .A(n225), .Q(output_wip[6]) );
    IN1 U160 ( .A(n227), .Q(output_wip[23]) );
    IN1 U161 ( .A(n229), .Q(output_wip[18]) );
    IN1 U162 ( .A(n231), .Q(output_wip[16]) );
    IN1 U163 ( .A(n233), .Q(output_wip[14]) );
    IN1 U164 ( .A(n235), .Q(output_wip[11]) );
    IN1 U165 ( .A(n237), .Q(output_wip[10]) );
    IN1 U166 ( .A(n239), .Q(output_wip[9]) );
    IN1 U167 ( .A(n241), .Q(output_wip[8]) );
    IN1 U168 ( .A(n243), .Q(output_wip[7]) );
    IN1 U169 ( .A(n245), .Q(output_wip[5]) );
    IN1 U170 ( .A(n247), .Q(output_wip[4]) );
    IN1 U171 ( .A(n249), .Q(output_wip[2]) );
    IN1 U172 ( .A(n251), .Q(output_wip[1]) );
    IN1 U173 ( .A(n257), .Q(output_fcs[24]) );
    IN3 U174 ( .A(n263), .Q(output_fcs[17]) );
    IN3 U175 ( .A(n269), .Q(output_fcs[23]) );
    DFA2 output_fcs_reg_31 ( .C(phi1), .D(input_fcs[31]), .Q(output_fcs[31]), 
        .RN(n188) );
    DFA2 output_fcs_reg_30 ( .C(phi1), .D(input_fcs[30]), .Q(output_fcs[30]), 
        .RN(n188) );
    DFA2 output_fcs_reg_29 ( .C(phi1), .D(input_fcs[29]), .Q(output_fcs[29]), 
        .RN(n188) );
    DFA2 output_fcs_reg_28 ( .C(phi1), .D(input_fcs[28]), .Q(output_fcs[28]), 
        .RN(n187) );
    DFA2 output_fcs_reg_26 ( .C(phi1), .D(input_fcs[26]), .Q(output_fcs[26]), 
        .RN(n188) );
    DFA2 output_fcs_reg_15 ( .C(phi1), .D(input_fcs[15]), .Q(output_fcs[15]), 
        .RN(n187) );
    DFA2 output_fcs_reg_14 ( .C(phi1), .D(input_fcs[14]), .Q(output_fcs[14]), 
        .RN(n187) );
    DFA2 output_fcs_reg_13 ( .C(phi1), .D(input_fcs[13]), .Q(output_fcs[13]), 
        .RN(n188) );
    DFA2 output_fcs_reg_12 ( .C(phi1), .D(input_fcs[12]), .Q(output_fcs[12]), 
        .RN(n188) );
    DFA2 output_fcs_reg_11 ( .C(phi1), .D(input_fcs[11]), .Q(output_fcs[11]), 
        .RN(n187) );
    DFA2 output_fcs_reg_10 ( .C(phi1), .D(input_fcs[10]), .Q(output_fcs[10]), 
        .RN(n187) );
    DFA2 output_fcs_reg_9 ( .C(phi1), .D(input_fcs[9]), .Q(output_fcs[9]), 
        .RN(n188) );
    DFA2 output_fcs_reg_8 ( .C(phi1), .D(input_fcs[8]), .Q(output_fcs[8]), 
        .RN(n188) );
    DFA2 output_fcs_reg_7 ( .C(phi1), .D(input_fcs[7]), .Q(output_fcs[7]), 
        .RN(n187) );
    DFA2 output_fcs_reg_6 ( .C(phi1), .D(input_fcs[6]), .Q(output_fcs[6]), 
        .RN(n188) );
    DFA2 output_fcs_reg_3 ( .C(phi1), .D(input_fcs[3]), .Q(output_fcs[3]), 
        .RN(n187) );
    DFA2 output_fcs_reg_2 ( .C(phi1), .D(input_fcs[2]), .Q(output_fcs[2]), 
        .RN(n187) );
    DFA2 output_fcs_reg_1 ( .C(phi1), .D(input_fcs[1]), .Q(output_fcs[1]), 
        .RN(n188) );
    DFA2 output_fcs_reg_0 ( .C(phi1), .D(input_fcs[0]), .Q(output_fcs[0]), 
        .RN(n188) );
    BU4 U176 ( .A(reset), .Q(n187) );
    BU8 U177 ( .A(n187), .Q(n188) );
    IN3 U178 ( .A(n189), .Q(output_wip[0]) );
    DFA2 output_wip_reg_0 ( .C(phi1), .D(input_wip[0]), .QN(n189), .RN(n188)
         );
    IN3 U179 ( .A(n191), .Q(output_wip[21]) );
    DFA2 output_wip_reg_21 ( .C(phi1), .D(input_wip[21]), .QN(n191), .RN(n188)
         );
    IN3 U180 ( .A(n193), .Q(output_wip[20]) );
    DFA2 output_wip_reg_20 ( .C(phi1), .D(input_wip[20]), .QN(n193), .RN(n188)
         );
    IN3 U181 ( .A(n195), .Q(output_wip[31]) );
    DFA2 output_wip_reg_31 ( .C(phi1), .D(input_wip[31]), .QN(n195), .RN(n188)
         );
    DFA2 output_wip_reg_30 ( .C(phi1), .D(input_wip[30]), .QN(n197), .RN(n188)
         );
    DFA2 output_wip_reg_29 ( .C(phi1), .D(input_wip[29]), .QN(n199), .RN(n187)
         );
    IN3 U182 ( .A(n201), .Q(output_wip[28]) );
    DFA2 output_wip_reg_28 ( .C(phi1), .D(input_wip[28]), .QN(n201), .RN(n187)
         );
    IN3 U183 ( .A(n205), .Q(output_wip[26]) );
    DFA2 output_wip_reg_26 ( .C(phi1), .D(input_wip[26]), .QN(n205), .RN(n188)
         );
    DFA2 output_wip_reg_25 ( .C(phi1), .D(input_wip[25]), .QN(n207), .RN(n187)
         );
    DFA2 output_wip_reg_19 ( .C(phi1), .D(input_wip[19]), .QN(n213), .RN(n187)
         );
    DFA2 output_wip_reg_17 ( .C(phi1), .D(input_wip[17]), .QN(n215), .RN(n187)
         );
    DFA2 output_wip_reg_3 ( .C(phi1), .D(input_wip[3]), .QN(n217), .RN(n187)
         );