crc_top_syn.v

一个verilog实现的crc校验

    IN1 U54 ( .A(reset), .Q(n88) );
    IN3 U55 ( .A(n88), .Q(n90) );
    DFA2 output_reg_6 ( .C(phi1), .D(\input [6]), .QN(n92), .RN(n90) );
    DFA2 output_reg_10 ( .C(phi1), .D(\input [10]), .QN(n98), .RN(n90) );
    DFA2 output_reg_0 ( .C(phi1), .D(\input [0]), .QN(n100), .RN(n90) );
    DFA2 output_reg_14 ( .C(phi1), .D(\input [14]), .QN(n102), .RN(n90) );
    DFA2 output_reg_13 ( .C(phi1), .D(\input [13]), .QN(n104), .RN(n90) );
    DFA2 output_reg_3 ( .C(phi1), .D(\input [3]), .QN(n106), .RN(n90) );
    IN4 U56 ( .A(n111), .Q(\output [15]) );
    DFA2 output_reg_15 ( .C(phi1), .D(\input [15]), .QN(n111), .RN(n90) );
    IN4 U57 ( .A(n115), .Q(\output [12]) );
    DFA2 output_reg_12 ( .C(phi1), .D(\input [12]), .QN(n115), .RN(n90) );
    IN4 U58 ( .A(n119), .Q(\output [4]) );
    DFA2 output_reg_4 ( .C(phi1), .D(\input [4]), .QN(n119), .RN(n90) );
    IN4 U59 ( .A(n123), .Q(\output [5]) );
    DFA2 output_reg_5 ( .C(phi1), .D(\input [5]), .QN(n123), .RN(n90) );
    IN4 U60 ( .A(n127), .Q(\output [2]) );
    DFA2 output_reg_2 ( .C(phi1), .D(\input [2]), .QN(n127), .RN(n90) );
    IN4 U61 ( .A(n131), .Q(\output [9]) );
    DFA2 output_reg_9 ( .C(phi1), .D(\input [9]), .QN(n131), .RN(n90) );
    IN4 U62 ( .A(n135), .Q(\output [11]) );
    DFA2 output_reg_11 ( .C(phi1), .D(\input [11]), .QN(n135), .RN(n90) );
    IN4 U63 ( .A(n139), .Q(\output [7]) );
    DFA2 output_reg_7 ( .C(phi1), .D(\input [7]), .QN(n139), .RN(n90) );
    IN4 U64 ( .A(n157), .Q(\output [1]) );
    DFA2 output_reg_1 ( .C(phi1), .D(\input [1]), .QN(n157), .RN(n90) );
    IN4 U65 ( .A(n159), .Q(\output [8]) );
    DFA2 output_reg_8 ( .C(phi1), .D(\input [8]), .QN(n159), .RN(n90) );
endmodule


module input_wait ( phi1, phi2, reset, \input , \output  );
output [15:0] \output ;
input  [15:0] \input ;
input  phi1, phi2, reset;
    wire btw1and2_12, btw1and2_7, btw6and7_11, btw3and4_9, btw4and5_1, 
        btw5and6_14, btw5and6_4, btw6and7_9, btw7and8_2, btw2and3_10, 
        btw2and3_3, btw7and8_12, btw3and4_7, btw3and4_0, btw4and5_14, 
        btw4and5_8, btw6and7_0, btw6and7_7, btw3and4_11, btw4and5_13, 
        btw1and2_15, btw1and2_9, btw2and3_4, btw7and8_15, btw5and6_3, 
        btw7and8_5, btw1and2_14, btw1and2_0, btw4and5_6, btw5and6_13, 
        btw1and2_13, btw1and2_8, btw7and8_4, btw1and2_6, btw1and2_1, 
        btw2and3_11, btw2and3_5, btw7and8_14, btw3and4_10, btw3and4_6, 
        btw4and5_12, btw6and7_6, btw4and5_7, btw5and6_12, btw3and4_8, 
        btw5and6_2, btw5and6_5, btw6and7_8, btw4and5_0, btw5and6_15, 
        btw3and4_1, btw6and7_10, btw4and5_15, btw6and7_1, btw4and5_9, 
        btw2and3_2, btw7and8_13, btw7and8_3, btw1and2_11, btw1and2_4, 
        btw2and3_9, btw6and7_12, btw7and8_8, btw4and5_2, btw5and6_7, 
        btw1and2_10, btw1and2_5, btw1and2_3, btw2and3_14, btw2and3_0, 
        btw7and8_11, btw7and8_1, btw3and4_15, btw2and3_13, btw3and4_4, 
        btw3and4_3, btw6and7_3, btw5and6_9, btw6and7_4, btw2and3_7, 
        btw3and4_12, btw4and5_10, btw4and5_5, btw5and6_10, btw5and6_0, 
        btw7and8_6, btw1and2_2, btw2and3_12, btw2and3_6, btw6and7_15, 
        btw7and8_7, btw3and4_13, btw3and4_5, btw4and5_11, btw5and6_8, 
        btw6and7_5, btw6and7_14, btw4and5_4, btw5and6_11, btw5and6_6, 
        btw5and6_1, btw2and3_8, btw4and5_3, btw2and3_15, btw3and4_14, 
        btw3and4_2, btw6and7_13, btw6and7_2, btw7and8_9, btw2and3_1, 
        btw7and8_10, btw7and8_0;
    input_phi2_register_3 Input1 ( .reset(reset), .phi2(phi2), .\input (
        \input ), .\output ({btw1and2_15, btw1and2_14, btw1and2_13, 
        btw1and2_12, btw1and2_11, btw1and2_10, btw1and2_9, btw1and2_8, 
        btw1and2_7, btw1and2_6, btw1and2_5, btw1and2_4, btw1and2_3, btw1and2_2, 
        btw1and2_1, btw1and2_0}) );
    input_phi1_register_3 Input8 ( .reset(reset), .phi1(phi1), .\input ({
        btw7and8_15, btw7and8_14, btw7and8_13, btw7and8_12, btw7and8_11, 
        btw7and8_10, btw7and8_9, btw7and8_8, btw7and8_7, btw7and8_6, 
        btw7and8_5, btw7and8_4, btw7and8_3, btw7and8_2, btw7and8_1, btw7and8_0
        }), .\output (\output ) );
    input_phi1_register_2 Input2 ( .reset(reset), .phi1(phi1), .\input ({
        btw1and2_15, btw1and2_14, btw1and2_13, btw1and2_12, btw1and2_11, 
        btw1and2_10, btw1and2_9, btw1and2_8, btw1and2_7, btw1and2_6, 
        btw1and2_5, btw1and2_4, btw1and2_3, btw1and2_2, btw1and2_1, btw1and2_0
        }), .\output ({btw2and3_15, btw2and3_14, btw2and3_13, btw2and3_12, 
        btw2and3_11, btw2and3_10, btw2and3_9, btw2and3_8, btw2and3_7, 
        btw2and3_6, btw2and3_5, btw2and3_4, btw2and3_3, btw2and3_2, btw2and3_1, 
        btw2and3_0}) );
    input_phi1_register_1 Input6 ( .reset(reset), .phi1(phi1), .\input ({
        btw5and6_15, btw5and6_14, btw5and6_13, btw5and6_12, btw5and6_11, 
        btw5and6_10, btw5and6_9, btw5and6_8, btw5and6_7, btw5and6_6, 
        btw5and6_5, btw5and6_4, btw5and6_3, btw5and6_2, btw5and6_1, btw5and6_0
        }), .\output ({btw6and7_15, btw6and7_14, btw6and7_13, btw6and7_12, 
        btw6and7_11, btw6and7_10, btw6and7_9, btw6and7_8, btw6and7_7, 
        btw6and7_6, btw6and7_5, btw6and7_4, btw6and7_3, btw6and7_2, btw6and7_1, 
        btw6and7_0}) );
    input_phi2_register_2 Input7 ( .reset(reset), .phi2(phi2), .\input ({
        btw6and7_15, btw6and7_14, btw6and7_13, btw6and7_12, btw6and7_11, 
        btw6and7_10, btw6and7_9, btw6and7_8, btw6and7_7, btw6and7_6, 
        btw6and7_5, btw6and7_4, btw6and7_3, btw6and7_2, btw6and7_1, btw6and7_0
        }), .\output ({btw7and8_15, btw7and8_14, btw7and8_13, btw7and8_12, 
        btw7and8_11, btw7and8_10, btw7and8_9, btw7and8_8, btw7and8_7, 
        btw7and8_6, btw7and8_5, btw7and8_4, btw7and8_3, btw7and8_2, btw7and8_1, 
        btw7and8_0}) );
    input_phi2_register_1 Input3 ( .reset(reset), .phi2(phi2), .\input ({
        btw2and3_15, btw2and3_14, btw2and3_13, btw2and3_12, btw2and3_11, 
        btw2and3_10, btw2and3_9, btw2and3_8, btw2and3_7, btw2and3_6, 
        btw2and3_5, btw2and3_4, btw2and3_3, btw2and3_2, btw2and3_1, btw2and3_0
        }), .\output ({btw3and4_15, btw3and4_14, btw3and4_13, btw3and4_12, 
        btw3and4_11, btw3and4_10, btw3and4_9, btw3and4_8, btw3and4_7, 
        btw3and4_6, btw3and4_5, btw3and4_4, btw3and4_3, btw3and4_2, btw3and4_1, 
        btw3and4_0}) );
    input_phi1_register_0 Input4 ( .reset(reset), .phi1(phi1), .\input ({
        btw3and4_15, btw3and4_14, btw3and4_13, btw3and4_12, btw3and4_11, 
        btw3and4_10, btw3and4_9, btw3and4_8, btw3and4_7, btw3and4_6, 
        btw3and4_5, btw3and4_4, btw3and4_3, btw3and4_2, btw3and4_1, btw3and4_0
        }), .\output ({btw4and5_15, btw4and5_14, btw4and5_13, btw4and5_12, 
        btw4and5_11, btw4and5_10, btw4and5_9, btw4and5_8, btw4and5_7, 
        btw4and5_6, btw4and5_5, btw4and5_4, btw4and5_3, btw4and5_2, btw4and5_1, 
        btw4and5_0}) );
    input_phi2_register_0 Input5 ( .reset(reset), .phi2(phi2), .\input ({
        btw4and5_15, btw4and5_14, btw4and5_13, btw4and5_12, btw4and5_11, 
        btw4and5_10, btw4and5_9, btw4and5_8, btw4and5_7, btw4and5_6, 
        btw4and5_5, btw4and5_4, btw4and5_3, btw4and5_2, btw4and5_1, btw4and5_0
        }), .\output ({btw5and6_15, btw5and6_14, btw5and6_13, btw5and6_12, 
        btw5and6_11, btw5and6_10, btw5and6_9, btw5and6_8, btw5and6_7, 
        btw5and6_6, btw5and6_5, btw5and6_4, btw5and6_3, btw5and6_2, btw5and6_1, 
        btw5and6_0}) );
endmodule


module gf_xor_input ( input_fcs, output_wip );
input  [31:0] input_fcs;
output [31:0] output_wip;
    wire net8524, output_wip_18, output_wip_3, net8460, output_wip_15, net6785, 
        output_wip_25, output_wip_12, output_wip_21, output_wip_16;
    assign output_wip[31] = output_wip_25;
    assign output_wip[30] = net6785;
    assign output_wip[25] = output_wip_25;
    assign output_wip[24] = net6785;
    assign output_wip[23] = output_wip_12;
    assign output_wip[21] = output_wip_21;
    assign output_wip[19] = output_wip_25;
    assign output_wip[18] = output_wip_18;
    assign output_wip[17] = net8460;
    assign output_wip[16] = output_wip_16;
    assign output_wip[15] = output_wip_15;
    assign output_wip[14] = output_wip_3;
    assign output_wip[13] = net8460;
    assign output_wip[12] = output_wip_12;
    assign output_wip[11] = output_wip_18;
    assign output_wip[10] = net8524;
    assign output_wip[9] = output_wip_16;
    assign output_wip[5] = output_wip_21;
    assign output_wip[4] = output_wip_15;
    assign output_wip[3] = output_wip_3;
    assign output_wip[2] = net8524;
    assign output_wip[1] = output_wip_16;
    EO1 U7 ( .A(input_fcs[30]), .B(input_fcs[29]), .Q(net8524) );
    EO1 U8 ( .A(input_fcs[30]), .B(input_fcs[29]), .Q(net8460) );
    EO1 U9 ( .A(input_fcs[30]), .B(input_fcs[26]), .Q(net6785) );
    EO1 U10 ( .A(input_fcs[24]), .B(input_fcs[28]), .Q(output_wip[28]) );
    EO1 U11 ( .A(input_fcs[26]), .B(input_fcs[22]), .Q(output_wip[26]) );
    EO1 U12 ( .A(input_fcs[26]), .B(input_fcs[28]), .Q(output_wip[0]) );
    EO1 U13 ( .A(input_fcs[30]), .B(input_fcs[31]), .Q(output_wip_18) );
    EO1 U14 ( .A(input_fcs[30]), .B(input_fcs[31]), .Q(output_wip_3) );
    EO1 U15 ( .A(input_fcs[27]), .B(input_fcs[23]), .Q(output_wip[27]) );
    EO1 U16 ( .A(input_fcs[28]), .B(input_fcs[25]), .Q(output_wip[20]) );
    EO1 U17 ( .A(input_fcs[28]), .B(input_fcs[27]), .Q(output_wip[8]) );
    EO1 U18 ( .A(input_fcs[30]), .B(input_fcs[28]), .Q(output_wip[22]) );
    EO1 U19 ( .A(input_fcs[30]), .B(input_fcs[27]), .Q(output_wip[6]) );
    EO1 U20 ( .A(input_fcs[29]), .B(input_fcs[25]), .Q(output_wip[29]) );
    EO1 U21 ( .A(input_fcs[29]), .B(input_fcs[28]), .Q(output_wip_16) );
    EO1 U22 ( .A(input_fcs[29]), .B(input_fcs[26]), .Q(output_wip_21) );
    EO1 U23 ( .A(input_fcs[31]), .B(input_fcs[26]), .Q(output_wip[7]) );
    EO1 U24 ( .A(input_fcs[29]), .B(input_fcs[31]), .Q(output_wip_12) );
    EO1 U25 ( .A(input_fcs[31]), .B(input_fcs[27]), .Q(output_wip_25) );
    EO1 U26 ( .A(input_fcs[28]), .B(input_fcs[31]), .Q(output_wip_15) );
endmodule


module gf_xor_2x ( input_wip, input_fcs, output_wip );
input  [31:0] input_wip;
input  [31:0] input_fcs;
output [31:0] output_wip;
    EO1 U7 ( .A(input_wip[15]), .B(input_fcs[25]), .Q(output_wip[15]) );
    EO1 U8 ( .A(input_wip[17]), .B(input_fcs[25]), .Q(output_wip[17]) );
    EO1 U9 ( .A(input_wip[10]), .B(input_fcs[25]), .Q(output_wip[10]) );
    EO1 U10 ( .A(input_wip[2]), .B(input_fcs[25]), .Q(output_wip[2]) );
    EO1 U11 ( .A(input_wip[21]), .B(input_fcs[25]), .Q(output_wip[21]) );
    EO1 U12 ( .A(input_wip[7]), .B(input_fcs[24]), .Q(output_wip[7]) );
    EO1 U13 ( .A(input_wip[30]), .B(input_fcs[24]), .Q(output_wip[30]) );
    EO1 U14 ( .A(input_wip[22]), .B(input_fcs[27]), .Q(output_wip[22]) );
    EO1 U15 ( .A(input_wip[19]), .B(input_fcs[24]), .Q(output_wip[19]) );
    EO1 U16 ( .A(input_wip[18]), .B(input_fcs[26]), .Q(output_wip[18]) );
    EO1 U17 ( .A(input_wip[14]), .B(input_fcs[27]), .Q(output_wip[14]) );
    EO1 U18 ( .A(input_wip[13]), .B(input_fcs[26]), .Q(output_wip[13]) );
    EO1 U19 ( .A(input_wip[8]), .B(input_fcs[26]), .Q(output_wip[8]) );
    EO1 U20 ( .A(input_wip[6]), .B(input_fcs[24]), .Q(output_wip[6]) );
    EO1 U21 ( .A(input_wip[1]), .B(input_fcs[27]), .Q(output_wip[1]) );
    EO1 U22 ( .A(input_wip[31]), .B(input_fcs[25]), .Q(output_wip[31]) );
    EO1 U23 ( .A(input_wip[0]), .B(input_fcs[25]), .Q(output_wip[0]) );
    EO1 U24 ( .A(input_wip[25]), .B(input_fcs[24]), .Q(output_wip[25]) );
    EO1 U25 ( .A(input_wip[20]), .B(input_fcs[24]), .Q(output_wip[20]) );
    EO1 U26 ( .A(input_wip[23]), .B(input_fcs[25]), .Q(output_wip[23]) );
    EO1 U27 ( .A(input_wip[28]), .B(input_fcs[22]), .Q(output_wip[28]) );
    EO1 U28 ( .A(input_wip[27]), .B(input_fcs[21]), .Q(output_wip[27]) );
    EO1 U29 ( .A(input_wip[26]), .B(input_fcs[20]), .Q(output_wip[26]) );
    EO1 U30 ( .A(input_wip[11]), .B(input_fcs[28]), .Q(output_wip[11]) );
    EO1 U31 ( .A(input_wip[24]), .B(input_fcs[23]), .Q(output_wip[24]) );
    EO1 U32 ( .A(input_wip[29]), .B(input_fcs[23]), .Q(output_wip[29]) );
    EO1 U33 ( .A(input_wip[5]), .B(input_fcs[23]), .Q(output_wip[5]) );
    EO1 U34 ( .A(input_wip[3]), .B(input_fcs[26]), .Q(output_wip[3]) );
    EO1 U35 ( .A(input_wip[16]), .B(input_fcs[24]), .Q(output_wip[16]) );
    EO1 U36 ( .A(input_wip[4]), .B(input_fcs[27]), .Q(output_wip[4]) );
    EO1 U37 ( .A(input_wip[9]), .B(input_fcs[27]), .Q(output_wip[9]) );
    EO1 U38 ( .A(input_wip[12]), .B(input_fcs[28]), .Q(output_wip[12]) );
endmodule


module gf_xor_3x ( input_wip, input_fcs, output_wip );
input  [31:0] input_wip;
input  [31:0] input_fcs;
output [31:0] output_wip;
    EO1 U7 ( .A(input_wip[6]), .B(input_fcs[23]), .Q(output_wip[6]) );
    EO1 U8 ( .A(input_wip[19]), .B(input_fcs[23]), .Q(output_wip[19]) );
    EO1 U9 ( .A(input_wip[18]), .B(input_fcs[23]), .Q(output_wip[18]) );
    EO1 U10 ( .A(input_wip[13]), .B(input_fcs[23]), .Q(output_wip[13]) );
    EO1 U11 ( .A(input_wip[7]), .B(input_fcs[23]), .Q(output_wip[7]) );
    EO1 U12 ( .A(input_wip[8]), .B(input_fcs[24]), .Q(output_wip[8]) );
    EO1 U13 ( .A(input_wip[4]), .B(input_fcs[24]), .Q(output_wip[4]) );
    EO1 U14 ( .A(input_wip[15]), .B(input_fcs[24]), .Q(output_wip[15]) );
    EO1 U15 ( .A(input_wip[14]), .B(input_fcs[24]), .Q(output_wip[14]) );
    EO1 U16 ( .A(input_wip[2]), .B(input_fcs[24]), .Q(output_wip[2]) );
    EO1 U17 ( .A(input_wip[9]), .B(input_fcs[25]), .Q(output_wip[9]) );
    EO1 U18 ( .A(input_wip[3]), .B(input_fcs[25]), .Q(output_wip[3]) );
    EO1 U19 ( .A(input_wip[12]), .B(input_fcs[25]), .Q(output_wip[12]) );
    EO1 U20 ( .A(input_wip[11]), .B(input_fcs[25]), .Q(output_wip[11]) );
    EO1 U21 ( .A(input_wip[1]), .B(input_fcs[25]), .Q(output_wip[1]) );
    EO1 U22 ( .A(input_wip[24]), .B(input_fcs[18]), .Q(output_wip[24]) );
    EO1 U23 ( .A(input_wip[20]), .B(input_fcs[20]), .Q(output_wip[20]) );
    EO1 U24 ( .A(input_fcs[20]), .B(input_wip[27]), .Q(output_wip[27]) );
    EO1 U25 ( .A(input_wip[25]), .B(input_fcs[19]), .Q(output_wip[25]) );
    EO1 U26 ( .A(input_fcs[19]), .B(input_wip[26]), .Q(output_wip[26]) );
    EO1 U27 ( .A(input_wip[10]), .B(input_fcs[21]), .Q(output_wip[10]) );
    EO1 U28 ( .A(input_wip[16]), .B(input_fcs[21]), .Q(output_wip[16]) );
    EO1 U29 ( .A(input_wip[21]), .B(input_fcs[21]), .Q(output_wip[21]) );
    EO1 U30 ( .A(input_fcs[21]), .B(input_wip[28]), .Q(output_wip[28]) );
    EO1 U31 ( .A(input_wip[0]), .B(input_fcs[22]), .Q(output_wip[0]) );
    EO1 U32 ( .A(input_wip[17]), .B(input_fcs[22]), .Q(output_wip[17]) );
    EO1 U33 ( .A(input_wip[23]), .B(input_fcs[22]), .Q(output_wip[23]) );
    EO1 U34 ( .A(input_fcs[22]), .B(input_wip[29]), .Q(output_wip[29]) );
    EO1 U35 ( .A(input_wip[5]), .B(input_fcs[22]), .Q(output_wip[5]) );
    EO1 U36 ( .A(input_fcs[23]), .B(input_wip[30]), .Q(output_wip[30]) );
    EO1 U37 ( .A(input_fcs[24]), .B(input_wip[31]), .Q(output_wip[31]) );
    EO1 U38 ( .A(input_fcs[25]), .B(input_wip[22]), .Q(output_wip[22]) );
endmodule


module gf_xor_4x ( input_wip, input_fcs, output_wip );
input  [31:0] input_wip;
input  [31:0] input_fcs;
output [31:0] output_wip;
    EO1 U7 ( .A(input_wip[5]), .B(input_fcs[21]), .Q(output_wip[5]) );
    EO1 U8 ( .A(input_wip[31]), .B(input_fcs[21]), .Q(output_wip[31]) );
    EO1 U9 ( .A(input_wip[30]), .B(input_fcs[20]), .Q(output_wip[30]) );
    EO1 U10 ( .A(input_wip[24]), .B(input_fcs[17]), .Q(output_wip[24]) );
    EO1 U11 ( .A(input_wip[19]), .B(input_fcs[19]), .Q(output_wip[19]) );
    EO1 U12 ( .A(input_wip[17]), .B(input_fcs[21]), .Q(output_wip[17]) );
    EO1 U13 ( .A(input_wip[15]), .B(input_fcs[23]), .Q(output_wip[15]) );
    EO1 U14 ( .A(input_wip[13]), .B(input_fcs[22]), .Q(output_wip[13]) );
    EO1 U15 ( .A(input_wip[12]), .B(input_fcs[22]), .Q(output_wip[12]) );
    EO1 U16 ( .A(input_wip[6]), .B(input_fcs[22]), .Q(output_wip[6]) );
    EO1 U17 ( .A(input_wip[23]), .B(input_fcs[17]), .Q(output_wip[23]) );
    EO1 U18 ( .A(input_wip[18]), .B(input_fcs[22]), .Q(output_wip[18]) );
    EO1 U19 ( .A(input_wip[16]), .B(input_fcs[20]), .Q(output_wip[16]) );
    EO1 U20 ( .A(input_wip[11]), .B(input_fcs[20]), .Q(output_wip[11]) );
    EO1 U21 ( .A(input_wip[10]), .B(input_fcs[19]), .Q(output_wip[10]) );