crc_top_syn.v

一个verilog实现的crc校验

module ff_reset ( phi2, reset_glitch, reset_clean );
input  phi2, reset_glitch;
output reset_clean;
    wire n15;
    IN8 U9 ( .A(n15), .Q(reset_clean) );
    DF8 reset_clean_reg ( .C(phi2), .D(reset_glitch), .QN(n15) );
endmodule


module input_phi2_register_0 ( reset, phi2, \input , \output  );
output [15:0] \output ;
input  [15:0] \input ;
input  reset, phi2;
    wire n75;
    DFA2 output_reg_15 ( .C(phi2), .D(\input [15]), .Q(\output [15]), .RN(n75)
         );
    DFA2 output_reg_14 ( .C(phi2), .D(\input [14]), .Q(\output [14]), .RN(n75)
         );
    DFA2 output_reg_13 ( .C(phi2), .D(\input [13]), .Q(\output [13]), .RN(n75)
         );
    DFA2 output_reg_12 ( .C(phi2), .D(\input [12]), .Q(\output [12]), .RN(n75)
         );
    DFA2 output_reg_11 ( .C(phi2), .D(\input [11]), .Q(\output [11]), .RN(n75)
         );
    DFA2 output_reg_10 ( .C(phi2), .D(\input [10]), .Q(\output [10]), .RN(n75)
         );
    DFA2 output_reg_9 ( .C(phi2), .D(\input [9]), .Q(\output [9]), .RN(n75) );
    DFA2 output_reg_8 ( .C(phi2), .D(\input [8]), .Q(\output [8]), .RN(n75) );
    DFA2 output_reg_7 ( .C(phi2), .D(\input [7]), .Q(\output [7]), .RN(n75) );
    DFA2 output_reg_6 ( .C(phi2), .D(\input [6]), .Q(\output [6]), .RN(n75) );
    DFA2 output_reg_5 ( .C(phi2), .D(\input [5]), .Q(\output [5]), .RN(n75) );
    DFA2 output_reg_4 ( .C(phi2), .D(\input [4]), .Q(\output [4]), .RN(n75) );
    DFA2 output_reg_3 ( .C(phi2), .D(\input [3]), .Q(\output [3]), .RN(n75) );
    DFA2 output_reg_2 ( .C(phi2), .D(\input [2]), .Q(\output [2]), .RN(n75) );
    DFA2 output_reg_1 ( .C(phi2), .D(\input [1]), .Q(\output [1]), .RN(n75) );
    DFA2 output_reg_0 ( .C(phi2), .D(\input [0]), .Q(\output [0]), .RN(n75) );
    BU4 U48 ( .A(reset), .Q(n75) );
endmodule


module input_phi2_register_1 ( reset, phi2, \input , \output  );
output [15:0] \output ;
input  [15:0] \input ;
input  reset, phi2;
    wire n82;
    DFA output_reg_15 ( .C(phi2), .D(\input [15]), .Q(\output [15]), .RN(n82)
         );
    DFA output_reg_14 ( .C(phi2), .D(\input [14]), .Q(\output [14]), .RN(n82)
         );
    DFA2 output_reg_13 ( .C(phi2), .D(\input [13]), .Q(\output [13]), .RN(
        reset) );
    DFA2 output_reg_12 ( .C(phi2), .D(\input [12]), .Q(\output [12]), .RN(
        reset) );
    DFA2 output_reg_11 ( .C(phi2), .D(\input [11]), .Q(\output [11]), .RN(
        reset) );
    DFA2 output_reg_10 ( .C(phi2), .D(\input [10]), .Q(\output [10]), .RN(
        reset) );
    DFA2 output_reg_9 ( .C(phi2), .D(\input [9]), .Q(\output [9]), .RN(reset)
         );
    DFA2 output_reg_8 ( .C(phi2), .D(\input [8]), .Q(\output [8]), .RN(reset)
         );
    DFA2 output_reg_7 ( .C(phi2), .D(\input [7]), .Q(\output [7]), .RN(reset)
         );
    DFA output_reg_6 ( .C(phi2), .D(\input [6]), .Q(\output [6]), .RN(n82) );
    DFA2 output_reg_5 ( .C(phi2), .D(\input [5]), .Q(\output [5]), .RN(reset)
         );
    DFA2 output_reg_4 ( .C(phi2), .D(\input [4]), .Q(\output [4]), .RN(reset)
         );
    DFA2 output_reg_3 ( .C(phi2), .D(\input [3]), .Q(\output [3]), .RN(reset)
         );
    DFA output_reg_2 ( .C(phi2), .D(\input [2]), .Q(\output [2]), .RN(n82) );
    DFA2 output_reg_1 ( .C(phi2), .D(\input [1]), .Q(\output [1]), .RN(reset)
         );
    DFA2 output_reg_0 ( .C(phi2), .D(\input [0]), .Q(\output [0]), .RN(reset)
         );
    BU2 U48 ( .A(reset), .Q(n82) );
endmodule


module input_phi2_register_2 ( reset, phi2, \input , \output  );
output [15:0] \output ;
input  [15:0] \input ;
input  reset, phi2;
    DFA2 output_reg_15 ( .C(phi2), .D(\input [15]), .Q(\output [15]), .RN(
        reset) );
    DFA2 output_reg_14 ( .C(phi2), .D(\input [14]), .Q(\output [14]), .RN(
        reset) );
    DFA2 output_reg_13 ( .C(phi2), .D(\input [13]), .Q(\output [13]), .RN(
        reset) );
    DFA2 output_reg_12 ( .C(phi2), .D(\input [12]), .Q(\output [12]), .RN(
        reset) );
    DFA2 output_reg_11 ( .C(phi2), .D(\input [11]), .Q(\output [11]), .RN(
        reset) );
    DFA2 output_reg_10 ( .C(phi2), .D(\input [10]), .Q(\output [10]), .RN(
        reset) );
    DFA2 output_reg_9 ( .C(phi2), .D(\input [9]), .Q(\output [9]), .RN(reset)
         );
    DFA2 output_reg_8 ( .C(phi2), .D(\input [8]), .Q(\output [8]), .RN(reset)
         );
    DFA2 output_reg_7 ( .C(phi2), .D(\input [7]), .Q(\output [7]), .RN(reset)
         );
    DFA2 output_reg_6 ( .C(phi2), .D(\input [6]), .Q(\output [6]), .RN(reset)
         );
    DFA2 output_reg_5 ( .C(phi2), .D(\input [5]), .Q(\output [5]), .RN(reset)
         );
    DFA output_reg_4 ( .C(phi2), .D(\input [4]), .Q(\output [4]), .RN(reset)
         );
    DFA output_reg_3 ( .C(phi2), .D(\input [3]), .Q(\output [3]), .RN(reset)
         );
    DFA output_reg_2 ( .C(phi2), .D(\input [2]), .Q(\output [2]), .RN(reset)
         );
    DFA output_reg_1 ( .C(phi2), .D(\input [1]), .Q(\output [1]), .RN(reset)
         );
    DFA output_reg_0 ( .C(phi2), .D(\input [0]), .Q(\output [0]), .RN(reset)
         );
endmodule


module input_phi2_register_3 ( reset, phi2, \input , \output  );
output [15:0] \output ;
input  [15:0] \input ;
input  reset, phi2;
    wire n97, n99;
    IN3 U48 ( .A(n97), .Q(n99) );
    DFA output_reg_15 ( .C(phi2), .D(\input [15]), .Q(\output [15]), .RN(n99)
         );
    DFA output_reg_14 ( .C(phi2), .D(\input [14]), .Q(\output [14]), .RN(n99)
         );
    DFA output_reg_13 ( .C(phi2), .D(\input [13]), .Q(\output [13]), .RN(n99)
         );
    DFA output_reg_12 ( .C(phi2), .D(\input [12]), .Q(\output [12]), .RN(n99)
         );
    DFA output_reg_11 ( .C(phi2), .D(\input [11]), .Q(\output [11]), .RN(n99)
         );
    DFA output_reg_10 ( .C(phi2), .D(\input [10]), .Q(\output [10]), .RN(n99)
         );
    DFA output_reg_9 ( .C(phi2), .D(\input [9]), .Q(\output [9]), .RN(n99) );
    DFA output_reg_8 ( .C(phi2), .D(\input [8]), .Q(\output [8]), .RN(n99) );
    DFA output_reg_7 ( .C(phi2), .D(\input [7]), .Q(\output [7]), .RN(n99) );
    DFA output_reg_6 ( .C(phi2), .D(\input [6]), .Q(\output [6]), .RN(n99) );
    DFA output_reg_5 ( .C(phi2), .D(\input [5]), .Q(\output [5]), .RN(n99) );
    DFA output_reg_4 ( .C(phi2), .D(\input [4]), .Q(\output [4]), .RN(n99) );
    DFA output_reg_3 ( .C(phi2), .D(\input [3]), .Q(\output [3]), .RN(n99) );
    DFA output_reg_2 ( .C(phi2), .D(\input [2]), .Q(\output [2]), .RN(n99) );
    DFA output_reg_1 ( .C(phi2), .D(\input [1]), .Q(\output [1]), .RN(n99) );
    DFA output_reg_0 ( .C(phi2), .D(\input [0]), .Q(\output [0]), .RN(n99) );
    IN1 U49 ( .A(reset), .Q(n97) );
endmodule


module input_phi1_register_0 ( reset, phi1, \input , \output  );
output [15:0] \output ;
input  [15:0] \input ;
input  reset, phi1;
    wire n76, n80;
    DFA2 output_reg_15 ( .C(phi1), .D(\input [15]), .Q(\output [15]), .RN(n80)
         );
    DFA2 output_reg_14 ( .C(phi1), .D(\input [14]), .Q(\output [14]), .RN(n80)
         );
    DFA2 output_reg_13 ( .C(phi1), .D(\input [13]), .Q(\output [13]), .RN(n80)
         );
    DFA2 output_reg_12 ( .C(phi1), .D(\input [12]), .Q(\output [12]), .RN(n80)
         );
    DFA2 output_reg_11 ( .C(phi1), .D(\input [11]), .Q(\output [11]), .RN(n80)
         );
    DFA2 output_reg_10 ( .C(phi1), .D(\input [10]), .Q(\output [10]), .RN(n80)
         );
    DFA2 output_reg_9 ( .C(phi1), .D(\input [9]), .Q(\output [9]), .RN(n80) );
    DFA2 output_reg_8 ( .C(phi1), .D(\input [8]), .Q(\output [8]), .RN(n80) );
    DFA2 output_reg_7 ( .C(phi1), .D(\input [7]), .Q(\output [7]), .RN(n80) );
    DFA2 output_reg_6 ( .C(phi1), .D(\input [6]), .Q(\output [6]), .RN(n80) );
    DFA2 output_reg_5 ( .C(phi1), .D(\input [5]), .Q(\output [5]), .RN(n80) );
    DFA2 output_reg_4 ( .C(phi1), .D(\input [4]), .Q(\output [4]), .RN(n80) );
    DFA2 output_reg_3 ( .C(phi1), .D(\input [3]), .Q(\output [3]), .RN(n80) );
    DFA2 output_reg_2 ( .C(phi1), .D(\input [2]), .Q(\output [2]), .RN(n80) );
    DFA2 output_reg_1 ( .C(phi1), .D(\input [1]), .Q(\output [1]), .RN(n80) );
    DFA2 output_reg_0 ( .C(phi1), .D(\input [0]), .Q(\output [0]), .RN(n80) );
    IN1 U48 ( .A(reset), .Q(n76) );
    IN3 U49 ( .A(n76), .Q(n80) );
endmodule


module input_phi1_register_1 ( reset, phi1, \input , \output  );
output [15:0] \output ;
input  [15:0] \input ;
input  reset, phi1;
    DFA2 output_reg_15 ( .C(phi1), .D(\input [15]), .Q(\output [15]), .RN(
        reset) );
    DFA2 output_reg_14 ( .C(phi1), .D(\input [14]), .Q(\output [14]), .RN(
        reset) );
    DFA2 output_reg_13 ( .C(phi1), .D(\input [13]), .Q(\output [13]), .RN(
        reset) );
    DFA2 output_reg_12 ( .C(phi1), .D(\input [12]), .Q(\output [12]), .RN(
        reset) );
    DFA2 output_reg_11 ( .C(phi1), .D(\input [11]), .Q(\output [11]), .RN(
        reset) );
    DFA2 output_reg_10 ( .C(phi1), .D(\input [10]), .Q(\output [10]), .RN(
        reset) );
    DFA2 output_reg_9 ( .C(phi1), .D(\input [9]), .Q(\output [9]), .RN(reset)
         );
    DFA2 output_reg_8 ( .C(phi1), .D(\input [8]), .Q(\output [8]), .RN(reset)
         );
    DFA2 output_reg_7 ( .C(phi1), .D(\input [7]), .Q(\output [7]), .RN(reset)
         );
    DFA2 output_reg_6 ( .C(phi1), .D(\input [6]), .Q(\output [6]), .RN(reset)
         );
    DFA2 output_reg_5 ( .C(phi1), .D(\input [5]), .Q(\output [5]), .RN(reset)
         );
    DFA2 output_reg_4 ( .C(phi1), .D(\input [4]), .Q(\output [4]), .RN(reset)
         );
    DFA2 output_reg_3 ( .C(phi1), .D(\input [3]), .Q(\output [3]), .RN(reset)
         );
    DFA2 output_reg_2 ( .C(phi1), .D(\input [2]), .Q(\output [2]), .RN(reset)
         );
    DFA2 output_reg_1 ( .C(phi1), .D(\input [1]), .Q(\output [1]), .RN(reset)
         );
    DFA2 output_reg_0 ( .C(phi1), .D(\input [0]), .Q(\output [0]), .RN(reset)
         );
endmodule


module input_phi1_register_2 ( reset, phi1, \input , \output  );
output [15:0] \output ;
input  [15:0] \input ;
input  reset, phi1;
    wire n84, n86;
    DFA2 output_reg_15 ( .C(phi1), .D(\input [15]), .Q(\output [15]), .RN(n86)
         );
    DFA2 output_reg_14 ( .C(phi1), .D(\input [14]), .Q(\output [14]), .RN(n86)
         );
    DFA2 output_reg_13 ( .C(phi1), .D(\input [13]), .Q(\output [13]), .RN(n86)
         );
    DFA2 output_reg_12 ( .C(phi1), .D(\input [12]), .Q(\output [12]), .RN(n86)
         );
    DFA2 output_reg_11 ( .C(phi1), .D(\input [11]), .Q(\output [11]), .RN(n86)
         );
    DFA2 output_reg_10 ( .C(phi1), .D(\input [10]), .Q(\output [10]), .RN(n86)
         );
    DFA2 output_reg_9 ( .C(phi1), .D(\input [9]), .Q(\output [9]), .RN(n86) );
    DFA2 output_reg_8 ( .C(phi1), .D(\input [8]), .Q(\output [8]), .RN(n86) );
    DFA2 output_reg_7 ( .C(phi1), .D(\input [7]), .Q(\output [7]), .RN(n86) );
    DFA2 output_reg_6 ( .C(phi1), .D(\input [6]), .Q(\output [6]), .RN(n86) );
    DFA2 output_reg_5 ( .C(phi1), .D(\input [5]), .Q(\output [5]), .RN(n86) );
    DFA2 output_reg_4 ( .C(phi1), .D(\input [4]), .Q(\output [4]), .RN(n86) );
    DFA2 output_reg_3 ( .C(phi1), .D(\input [3]), .Q(\output [3]), .RN(n86) );
    DFA2 output_reg_2 ( .C(phi1), .D(\input [2]), .Q(\output [2]), .RN(n86) );
    DFA2 output_reg_1 ( .C(phi1), .D(\input [1]), .Q(\output [1]), .RN(n86) );
    DFA2 output_reg_0 ( .C(phi1), .D(\input [0]), .Q(\output [0]), .RN(n86) );
    IN1 U48 ( .A(reset), .Q(n84) );
    IN3 U49 ( .A(n84), .Q(n86) );
endmodule


module input_phi1_register_3 ( reset, phi1, \input , \output  );
output [15:0] \output ;
input  [15:0] \input ;
input  reset, phi1;
    wire n88, n90, n92, n98, n100, n102, n104, n106, n111, n115, n119, n123, 
        n127, n131, n135, n139, n157, n159;
    IN3 U48 ( .A(n92), .Q(\output [6]) );
    IN3 U49 ( .A(n98), .Q(\output [10]) );
    IN3 U50 ( .A(n100), .Q(\output [0]) );
    IN3 U51 ( .A(n102), .Q(\output [14]) );
    IN3 U52 ( .A(n104), .Q(\output [13]) );
    IN3 U53 ( .A(n106), .Q(\output [3]) );