.synopsys_vss.setup

一个verilog实现的crc校验

EDITCMD	= vi
TIMEBASE = ns
CS_CCPATH = /usr/local/bin/gcc


DEFAULT	:	   $SYNOPSYS_DESIGN_LIB/WORK
POSTSYN :          $SYNOPSYS_DESIGN_LIB/POSTSYN

csx_HRDLIB : /usr/local-tde/cad1/amslibs/v3.20/vital/csx_3.3V/HRDLIB9910
csx_IOLIB_3M : /usr/local-tde/cad1/amslibs/v3.20/vital/csx_3.3V/IOLIB3M9910


USE =   .\
        ./vhdl\
        $SYNOPSYS/packages/synopsys/src\
        $SYNOPSYS/packages/IEEE/src\
        $SYNOPSYS/packages/IEEE_asic/src\
        $SYNOPSYS/packages/mvl_7/src\
        $SYNOPSYS/packages/mvl7_asic/src\
        $SYNOPSYS/packages/comdisco/src\
        $SYNOPSYS/packages/gtech/src\
        $SYNOPSYS/packages/gscomp/src\
        $SYNOPSYS/packages/dware/src\
        $SYNOPSYS/packages/CD/src\
        $SYNOPSYS/packages/UI/src\
        $SYNOPSYS/packages/VHDLGEN/src\
        $SYNOPSYS/dw/dw01/src\
        $SYNOPSYS/dw/dw02/src\
        $SYNOPSYS/dw/dw03/src\
        $SYNOPSYS/dw/dw04/src\
        $SYNOPSYS/dw/dw05/src\ 
        $SYNOPSYS/dw/dw06/src\
        $SYNOPSYS/dw/dw07/src