.synopsys_dc.setup

一个verilog实现的crc校验

designer = "tde"
company = "TdE LUND"

cache_read  = ./;
cache_write = ./;


search_path = { /usr/local-tde/cad1/amslibs/v3.20/synopsys/csx_3.3V } + search_path

link_library = { csx_HRDLIB.db csx_IOLIB_3M.db standard.sldb dw01.sldb dw02.sldb}
target_library = { csx_HRDLIB.db csx_IOLIB_3M.db }
symbol_library = { csxs.sdb };
synthetic_library = { standard.sldb dw01.sldb dw02.sldb }

verilogout_no_tri = true
bus_naming_style = "%s_%d"
bus_dimension_separator_style = "_"

define_name_rules opus -reserved_words {"disable", "abs", "access", "after", \
  "alias", "all", "and", "architecture", "array", "assert", "attribute", \
  "begin", "block", "body", "buffer", "bus", "case", "component", \
  "configuration", "constant", "disconnect", "downto", "else", "elsif", \
  "end", "entity", "exit", "file", "for", "function", "generate", "generic", \
  "guarded", "if", "in", "inout", "is", "label", "library", "linkage", \
  "loop", "map", "mod", "nand", "new", "next", "nor", "not", "null",  "of", \
  "on", "open", "or", "others", "out", "overflow", "package", "port", "procedure", \
  "process", "range", "record", "register", "rem", "report", "return", \
  "select", "severity", "sign", "signal", "subtype", "then", "to", "transport", \
  "type", "units", "until", "use", "variable", "wait", "when", "while", \
  "with", "xor"} \
  -allowed "A-Z a-z _ 0-9" -first_restricted "0-9 _" -last_restricted "_" \
  -case_insensitive -collapse_name_space -replacement_char "X"
 
vhdlout_bit_type = "std_logic"
vhdlout_bit_vector_type = "std_logic_vector"
vhdlout_single_bit = "VECTOR"
vhdlout_preserve_hierarchical_types = "VECTOR"
vhdlout_dont_write_types = true
vhdlout_write_components = true
vhdlout_use_packages = { \
                         "IEEE.std_logic_1164", \
                         "IEEE.std_logic_arith", \
                         "csx_HRDLIB.Vcomponents", \
                         "csx_IOLIB_3M.Vcomponents" \
                        }