v2html

v2html - verilog to html converter 主要为FPGA和ASIC工作人员

#
sub print_module_index {
    my ($out,$fdata,$data) = @_;
    my ($qword,$title,$inst,$m,$f,$i,$file,$inst_by,$tasks,$funcs,@t_and_f,$tf,$t_type,
	$comma,$fcomma,$m_line,$type);

    ($file,$m_line)=&rvp::get_modules_file($fdata,$data);
    $type=&rvp::get_modules_type($fdata,$data);
    $qword=$data; quote_html(\$qword);
    $title  = "<b><a name=\"$data\"></a>".
	"<a $frame_middle href=\"".
	    hfile($file,$m_line)."#$data\">$qword</a></b>\n";
    $title .= "<i>($type)</i>\n" unless $type eq 'module';

    $inst=$comma='';
    ($m,$f,$i) = &rvp::get_first_instantiation($fdata,$data );
    while ($m) {
	if (&rvp::module_exists($fdata,$m)) {
	    $inst.="$comma<a href=\"".index_link("Modules",$m)."\">$m:$i</a>&nbsp;";
	}
	else {
	    $inst.="$comma$m:$i&nbsp;";
	}
	$comma=', ';
	($m,$f,$i) = &rvp::get_next_instantiation($fdata);
    }

    $inst_by=$comma='';
    ($m,$f,$i) = &rvp::get_first_instantiator($fdata,$data );
    while ($m) {
	if (&rvp::module_exists($fdata,$m)) {
	    $inst_by.="$comma<a href=\"".index_link("Modules",$m)."\">$m:$i</a>&nbsp;";
	}
	else {
	    $inst_by.="$comma$m:$i&nbsp;";
	}
	$comma=', ';
	($m,$f,$i) = &rvp::get_next_instantiator($fdata);
    }


    $tasks=$funcs=$comma=$fcomma='';
    if ( @t_and_f = &rvp::get_modules_t_and_f($fdata,$data) ) {
	foreach $tf (sort @t_and_f) {
	    ($t_type)=&rvp::get_modules_t_or_f($fdata,$data,$tf);
	    if ($t_type eq 'function') { 
		$funcs.="$fcomma<a href=\"".index_link("Functions","${tf}___$data").
		    "\">$tf<\/a>&nbsp;";  
		$fcomma=', ';
	    }
	    else { 
		$tasks.="$comma<a href=\"".index_link("Tasks","${tf}___$data").
		    "\">$tf<\/a>&nbsp;";
		$comma=', ';
	    }
	}
    }


    print_itable( $out , $title ,
		 [ "File:" , "<a href=\"".index_link("Files",$file)."\">$file</a>" .
		            ((&rvp::module_ignored($fdata,$data)) ?
                              " (Warning: Duplicate definition found)" : "") ,
		   "Instantiates:" , $inst ,
		   "Instantiated by:" , $inst_by,
		   "Tasks:"           , $tasks , 
		   "Functions:"       , $funcs ]);

}

###############################################################################
# Called to print on entry in the Signal index
#
sub print_signal_index {
    my ($out,$fdata,$data) = @_;
    my ($qword,$sig,$m,$title,$s_line,$s_i_line,$s_type,$s_file,
	$s_pos,$s_neg,$s_type2,$im,$in,$p,$port_con,$comma,$con_to,$cts,$cti,$ctm);

    ($sig,$m) = split(' ',$data);

    ($s_line,undef,$s_i_line,$s_type,$s_file,$s_pos,$s_neg,$s_type2) = 
	&rvp::get_module_signal($fdata,$m,$sig);
    $s_type.=" $s_type2" if $s_type2;
    $s_type.=" (used in \@posedge)" if $s_pos;
    $s_type.=" (used in \@negedge)" if $s_neg;

    $qword="$sig : $m"; quote_html(\$qword);
    $title  = "<b><a name=\"$sig"."___$m\"></a>".
	"<a $frame_middle href=\"".
	    hfile($s_file,$s_line)."#$s_line\">$qword</a></b> : $s_type";

    $port_con=$comma='';
    ($im,$in,$p,)=&rvp::get_first_signal_port_con($fdata,$m,$sig);
    while ($im) {
	if (&rvp::module_exists($fdata,$im) && ($p !~ m/^[0-9]/)) {
	    $port_con.="$comma<a href=\"".index_link("Signals","${p}___$im")."\">$im:$in:$p</a>&nbsp;";
	}
	else { $port_con.="$comma$im:$in:$p&nbsp;"; }
	$comma=', ';
	($im,$in,$p,)=&rvp::get_next_signal_port_con($fdata);
    }
    
    $con_to=$comma='';
    ($cts,$ctm,$cti)=&rvp::get_first_signal_con_to($fdata,$m,$sig);
    while ($cts) {
	if (&rvp::module_exists($fdata,$ctm) && ($cts !~ m/^[0-9]/)) {
	    $con_to.="$comma<a href=\"".index_link("Signals","${cts}___$ctm")."\">$ctm:$cti:$cts</a>&nbsp;";
	}
	else { $con_to.="$comma$ctm:$cti:$cts&nbsp;"; }
	$comma=', ';
	($cts,$ctm,$cti)=&rvp::get_next_signal_con_to($fdata);
    }

    # Only print table if there are some portcons to save space
    if ($port_con || $con_to) {
	print_itable( $out , $title ,
		      [ "Connects down to:" , $port_con ,
		        "Connects up to:" , $con_to ]);
    }
    else {
	print_itable( $out , $title , []);
    }

}

###############################################################################
# Called to print on entry in the Tasks or Functions index
#
sub print_tf_index {
    my ($out,$fdata,$data) = @_;
    my ($qword,$tf,$m,$title,$t_type,$t_line ,$t_file,$t_anchor);

    ($tf,$m) = split(' ',$data);

    ($t_type,$t_line ,$t_file,$t_anchor)=&rvp::get_modules_t_or_f($fdata,$m,$tf);


    $qword="$tf"; quote_html(\$qword);
    $title  = "<b><a name=\"$tf"."___$m\"></a>".
	"<a $frame_middle href=\"".
	    hfile($t_file,$t_line)."#$t_anchor\">$qword</a></b>";

    print_itable( $out , $title , 
		 [ "File:" , "<a href=\"".index_link("Files",$t_file).
		  "\">$t_file</a>" , 
		  "Module:" , "<a href=\"".index_link("Modules",$m)."\">$m</a>" ]);

}

###############################################################################
# Print out a table in the index, called with the output file, the title and
#  a pointer to an array of table pairs (column 1 and column 2)
#
sub print_itable {
    my ($out,$title,$tab) = @_;
    my ($f1,$f2,$empty);
    print $out "&nbsp;$title\n";
    if (@{$tab}) {
	$empty=1;
	print $out "<div align=right><table cols=2 width=\"97%\">\n";
	while ($f1=shift(@{$tab})) {
	    $f2=shift(@{$tab});
	    die "print_itable internal error" unless (defined($f2));
	    if ($f2 ne '') {
		$empty=0;
		print $out "<tr><td valign=top width=\"17%\"><i>$f1</i></td>".
		    "<td valign=top width=\"83%\">$f2</td></tr>\n";
	    }
	}
	print $out "<tr><td></td></tr>\n" if ($empty); # NS does not like empty tables
	print $out "</table></div>\n";
    }
    else {
	print $out "<br>\n";
    }
}

sub index_link {
    my ($type,$elem) = @_;

    # debugging checks
    print "Error: Bad index link $type $elem\n" 
    	unless (exists($index_info->{$type}{letters}{uc(substr($elem,0,1))}));
    return $index_info->{$type}{letters}{uc(substr($elem,0,1))} . "#$elem";
}

###############################################################################
#   Hierarchy and frame printing
###############################################################################

###############################################################################
# Print out the hierarchy
#  arguments: output_file_name, javascript flag
#
sub print_hier {
    my ($h_file,$js,$hier_tops_p) = @_;
    my ($out_file,$m,$imod);
    local (*HIER,*JSF,*FT);

    # write out the blank printIt file - this is a work around for a NS6 bug (22681)
    open(FT,">$out_dir"."blank_printIt.html") || 
	die "Error: can not open file blank_printIt.html to write: $!\n ";
    push(@output_files,"$out_dir"."blank_printIt.html");
    print FT "<html><head>\n";
    print FT "<title></title>\n";
    print FT $style_sheet_link;
    print FT "</head><body onload=\"javascript:parent.printIt('',-1)\"></body></html>\n";
    close (FT);


    $out_file = $out_dir . $h_file;
    open(HIER,">$out_file") || 
	die "Error: can not open file $out_file to write: $!\n";
    push(@output_files,"$out_file");

    if (defined(@{$hier_tops_p})) {
        # check that all the hierarchy tops (specified with -ht)  exist
	foreach $module (@{$hier_tops_p}) {
	    die "Error: Did not find top module $module\n"
		if (!&rvp::module_exists($verilog_db,$module));
	}
    }
    else {
	# search for all hier tops - modules that are not instantiated
	#  but do instantiate at least one module that we have source for
	MOD_LOOP: foreach $m (sort &rvp::get_modules($verilog_db)) {
	    print "  checking if module $m is a top\n" if $debug;
	    if  (! &rvp::get_first_instantiator($verilog_db,$m)) {
		($imod) = &rvp::get_first_instantiation($verilog_db,$m );
		while ($imod) {
		    print "   checking instantiation $imod\n" if $debug;
		    if (&rvp::module_exists($verilog_db,$imod)) {
			push(@{$hier_tops_p},$m);
			next MOD_LOOP;
		    }
		    ($imod) = &rvp::get_next_instantiation($verilog_db);
		}
	    }
	}
    }

    if ($js) {
	print " doing js version\n" if $debug;
	$js_file = $out_file;
	$js_file =~ s/.html$//;
	$js_file = $js_file . ".js";
	open(JSF,">$js_file") || 
	    die "Error: can not open file $js_file to write: $!\n";

	# do the java script version first
	print_js_hier_head(*JSF,join(" ",@{$hier_tops_p}));
	print_hier_body(*JSF,$hier_tops_p,1);
	print_js_hier_tail(*JSF);
	close(JSF);
    }

    # now do the html version
    print " doing html version\n" if $debug;
    print_hier_head(*HIER,join(" ",@{$hier_tops_p}),$js,$js_file,$h_file);
    print_hier_body(*HIER,$hier_tops_p,0);
    print_hier_tail(*HIER,$js);
    close(HIER);
    print " done html version\n" if $debug;
}

###############################################################################
# Print out header information in hierarchy file
#
sub print_hier_head {
    my ($out,$t,$js,$js_file,$h_file) = @_;

    print " print_hier_head\n" if $debug;
    print $out "<!-- v2html hierarchy ";
    print $out "K=$cgi_key " if $cgi_script;
    print $out "-->\n";
    print $out "<html><head>\n";
    
    if ($js) {
	print_js_include( $out , $js_file);
	unlink($js_file) unless $frames; # do not need the javascript file anymore
    }

    print $out "<title>hierarchy: $t</title>\n";
    print $out $style_sheet_link;
    print $out "</head>\n";

    print $out "<noscript>" if ($js);

    print $out "<body>\n";


    print $out "<center><b>The Javascript features of this page are not ".
	"working in your browser. Either you do not have a Javascript capable".
	    " browser (NS3, IE4 or later) or you have Javascript".
		" disabled in your preferences.</b></center><br>"
		if ($js);
}

###############################################################################
# Print out the hierarchy
#  arguments: output_file_name, javascript flag
#
sub print_hier_body {
    my ($out,$hier_tops_p,$js) = @_;
    my ($f,$m,$m_line,$fb,@no_mods,$nm,@unconnected,$imod);

    print " print_hier_body\n" if $debug;
    $ul_id=0; # used for folding hierarchy

    print_navbar($out,$js,'Hierarchy',\%navbar,'','',$vert_frames);
    print_h_or_js($out, "<center><h3>$hier_comment</h3></center>\n",$js) if $hier_comment;

    #
    # Go through each module you were asked for
    #
    foreach $m (@{$hier_tops_p}) {
	($f,$m_line) = &rvp::get_modules_file($verilog_db,$m);
	print_h_or_js($out, "<h3>Hierarchy for " . $m . "</h3>\n",$js);
	print_h_or_js($out, "<nobr><ul>\n",$js);
	print_tree($out,$m,$m_line,$f,0,1,$js);
	print_h_or_js($out, "</ul></nobr>\n",$js);
	print_h_or_js($out, "<hr>\n",$js);
    }

    # 
    # now do files containing no modules
    #
    if ($print_no_mods) {
	foreach $f (&rvp::get_files($verilog_db)) {
	    push(@no_mods,$f) 
		if (0 == &rvp::get_files_modules($verilog_db,$f));
	}
	if (@no_mods) {
	    print_h_or_js($out, "<h3>Files containing no modules</h3>\n",$js);
	    print_h_or_js($out, "<ul>\n",$js);
	    foreach $f (@no_mods) {
		($fb = $f) =~ s/^.*\///;
		print_h_or_js($out, "<li>" . "<a $frame_code href=\"" 
			      . hfile($f,1) . "\">$fb</a>\n",$js);
		if ($output_index) {
		    print_h_or_js($out,"<a $frame_code href=\"".
				  index_link("Files",$fb)."\">$icon_i<\/a>\n",$js);
		}
	    }
	    print_h_or_js($out, "</ul>\n",$js);
	    print_h_or_js($out, "<hr>\n",$js);
	}
    }

    #
    # Now do unconnected modules
    #  (unreffed modules that do not instantiate any other modules
    #   that we have source for)
    #
    if ($print_unconnected) {
	MOD_LOOP: foreach $m (sort &rvp::get_modules($verilog_db)) {
	    print "  checking if module $m is unconnected\n" if $debug;
	    # the hier tops have been done already, so ignore them
	    foreach $imod (@{$hier_tops_p}) {
		if ($imod eq $m) { next MOD_LOOP; }
	    }
	    if  ( ! &rvp::get_first_instantiator($verilog_db,$m)) {
		($imod) = &rvp::get_first_instantiation($verilog_db,$m );
		while ($imod) { 
		    if (&rvp::module_exists($verilog_db,$imod)) {
			next MOD_LOOP;
		    }
		    ($imod) = &rvp::get_next_instantiation($verilog_db );
		} 
		# if we got here we are unconnected
		push(@unconnected,$m);
	    }
	}
	if (scalar(@unconnected) != 0) {
	    if ((scalar(@unconnected) == 1)&&(!defined(@{$hier_tops_p}))) { 
		print_h_or_js($out, "<h3>$unconnected[0]</h3>\n",$js);
	    }
	    else {
		print_h_or_js($out, "<h3>Unconnected modules</h3>\n",$js);
	    }
	    
	    print_h_or_js($out, "<nobr><ul>\n",$js);
	    foreach $m (@unconnected) {
		# even though we're unconnected print_tree is called
		#  because there may be submodules we do not have source for
		($f,$m_line) = &rvp::get_modules_file($verilog_db,$m);
		print_tree($out,$m,$m_line,$f,0,1,$js);
	    }
	    print_h_or_js($out, "</ul></nobr>\n",$js);
	    print_h_or_js($out, "<hr>\n",$js);
	}
    }
}

###############################################################################
# Recursively Print the hierarchical tree for a module
#
sub print_tree {
    my ($out,$m,$m_line,$f,$depth,$n_inst,$js) = @_;
    my (@t,$tt,$count,$this_ul_id,$this_ces_arg,$prev_ces_arg,$i,$imod,$tl,$tf);

    print " print_hier_tree($out,$m,$m_line,$f,$depth,$n_inst,$js)\n" if $debug;
    if ($js) {
	if ( defined($index_stack[0]) ) {
	    $prev_ces_arg = "ul_i_" . $index_stack[$#index_stack];
	}
	else {