state_machine.map.rpt

verilog HDL 基础实验源码

+---------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                   ;
+----------------------------+------------+------+--------------------------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name                  ;
+----------------------------+------------+------+--------------------------------------+
; |state_machine             ; 43         ; 18   ; |state_machine                       ;
;    |lpm_counter:cnt_rtl_0| ; 24         ; 0    ; |state_machine|lpm_counter:cnt_rtl_0 ;
+----------------------------+------------+------+--------------------------------------+


+-----------------------------------------------+
; State Machine - |state_machine|state          ;
+--------------+----------+----------+----------+
; Name         ; state~48 ; state~47 ; state~46 ;
+--------------+----------+----------+----------+
; state.state0 ; 0        ; 0        ; 0        ;
; state.state6 ; 1        ; 1        ; 0        ;
; state.state5 ; 1        ; 0        ; 1        ;
; state.state4 ; 1        ; 0        ; 0        ;
; state.state3 ; 0        ; 1        ; 1        ;
; state.state2 ; 0        ; 1        ; 0        ;
; state.state1 ; 0        ; 0        ; 1        ;
; state.state7 ; 1        ; 1        ; 1        ;
+--------------+----------+----------+----------+


+-------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |state_machine ;
+----------------+-------+------------------------------------------------------+
; Parameter Name ; Value ; Type                                                 ;
+----------------+-------+------------------------------------------------------+
; state0         ; 000   ; Binary                                               ;
; state1         ; 001   ; Binary                                               ;
; state2         ; 010   ; Binary                                               ;
; state3         ; 011   ; Binary                                               ;
; state4         ; 100   ; Binary                                               ;
; state5         ; 101   ; Binary                                               ;
; state6         ; 110   ; Binary                                               ;
; state7         ; 111   ; Binary                                               ;
+----------------+-------+------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:cnt_rtl_0 ;
+------------------------+----------+------------------------------------+
; Parameter Name         ; Value    ; Type                               ;
+------------------------+----------+------------------------------------+
; AUTO_CARRY_CHAINS      ; ON       ; AUTO_CARRY                         ;
; IGNORE_CARRY_BUFFERS   ; OFF      ; IGNORE_CARRY                       ;
; AUTO_CASCADE_CHAINS    ; ON       ; AUTO_CASCADE                       ;
; IGNORE_CASCADE_BUFFERS ; OFF      ; IGNORE_CASCADE                     ;
; LPM_WIDTH              ; 24       ; Untyped                            ;
; LPM_DIRECTION          ; UP       ; Untyped                            ;
; LPM_MODULUS            ; 0        ; Untyped                            ;
; LPM_AVALUE             ; UNUSED   ; Untyped                            ;
; LPM_SVALUE             ; UNUSED   ; Untyped                            ;
; DEVICE_FAMILY          ; MAX7000S ; Untyped                            ;
; CARRY_CHAIN            ; MANUAL   ; Untyped                            ;
; CARRY_CHAIN_LENGTH     ; 48       ; CARRY_CHAIN_LENGTH                 ;
; NOT_GATE_PUSH_BACK     ; ON       ; NOT_GATE_PUSH_BACK                 ;
; CARRY_CNT_EN           ; SMART    ; Untyped                            ;
; LABWIDE_SCLR           ; ON       ; Untyped                            ;
; USE_NEW_VERSION        ; TRUE     ; Untyped                            ;
; CBXI_PARAMETER         ; NOTHING  ; Untyped                            ;
+------------------------+----------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Dec 14 11:11:30 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off state_machine -c state_machine
Info: Found 1 design units, including 1 entities, in source file state_machine.v
    Info: Found entity 1: state_machine
Info: Elaborating entity "state_machine" for the top level hierarchy
Warning: Verilog HDL assignment warning at state_machine.v(25): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at state_machine.v(31): truncated value with size 32 to match size of target (24)
Warning: Verilog HDL assignment warning at state_machine.v(34): truncated value with size 32 to match size of target (24)
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=24) from the following logic: "cnt[0]~0"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: State machine "|state_machine|state" contains 8 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|state_machine|state"
Info: Encoding result for state machine "|state_machine|state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "state~48"
        Info: Encoded state bit "state~47"
        Info: Encoded state bit "state~46"
    Info: State "|state_machine|state.state0" uses code string "000"
    Info: State "|state_machine|state.state6" uses code string "110"
    Info: State "|state_machine|state.state5" uses code string "101"
    Info: State "|state_machine|state.state4" uses code string "100"
    Info: State "|state_machine|state.state3" uses code string "011"
    Info: State "|state_machine|state.state2" uses code string "010"
    Info: State "|state_machine|state.state1" uses code string "001"
    Info: State "|state_machine|state.state7" uses code string "111"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "c[0]" stuck at VCC
    Warning: Pin "en[0]" stuck at GND
    Warning: Pin "en[1]" stuck at GND
    Warning: Pin "en[2]" stuck at GND
    Warning: Pin "en[3]" stuck at GND
    Warning: Pin "en[4]" stuck at GND
    Warning: Pin "en[5]" stuck at GND
    Warning: Pin "en[6]" stuck at GND
    Warning: Pin "en[7]" stuck at GND
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
    Info: Promoted clear signal driven by pin "rst" to global clear signal
Info: Implemented 61 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 16 output pins
    Info: Implemented 43 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings
    Info: Processing ended: Wed Dec 14 11:11:33 2005
    Info: Elapsed time: 00:00:03