📄 add.fit.rpt
字号:
; ~GND~0 ; 1 ;
; ~VCC~0 ; 1 ;
; reduce_or~2904 ; 1 ;
; reduce_or~2898 ; 1 ;
; reduce_or~2892 ; 1 ;
; reduce_or~2890 ; 1 ;
; reduce_or~2885 ; 1 ;
; reduce_or~2879 ; 1 ;
; reduce_or~2873 ; 1 ;
; reduce_or~2869 ; 1 ;
; reduce_or~2862 ; 1 ;
; reduce_or~2861 ; 1 ;
; reduce_or~2855 ; 1 ;
; reduce_or~2848 ; 1 ;
; reduce_or~2839 ; 1 ;
; reduce_or~2837 ; 1 ;
; reduce_or~2831 ; 1 ;
; reduce_or~2824 ; 1 ;
; reduce_or~2810 ; 1 ;
; reduce_or~2804 ; 1 ;
; reduce_or~2803 ; 1 ;
; reduce_or~2802 ; 1 ;
; reduce_or~2800 ; 1 ;
+---------------------+-----------+
+-----------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 16 / 288 ( 5 % ) ;
; PIAs ; 16 / 288 ( 5 % ) ;
+----------------------------+------------------+
+----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 2.00) ; Number of LABs (Total = 2) ;
+----------------------------------------------+-----------------------------+
; 0 ; 6 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 2.63) ; Number of LABs (Total = 3) ;
+----------------------------------------+-----------------------------+
; 0 ; 5 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 11 ; 1 ;
+----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 4 ;
; 2 ; 2 ;
+--------------------------+------------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 0.88) ; Number of LABs (Total = 2) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 6 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
+-------------------------------------------------+-----------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+
; F ; LC86 ; reduce_or~2818bal, reduce_or~2823bal, reduce_or~2817sexp5 ; c[2] ;
; F ; LC94 ; ; c[0] ;
; F ; LC93 ; b[0], a[1], a[2], b[2], b[1], reduce_or~2831, reduce_or~2837 ; c[4] ;
; F ; LC84 ; reduce_or~2898, b[0], b[1], a[2], b[2], a[0], a[1] ; reduce_or~2862 ;
; F ; LC88 ; reduce_or~2885, b[1], b[0], a[0], a[1], a[2], b[2], reduce_or~2910 ; c[7] ;
; F ; LC91 ; reduce_or~2892, a[2], b[2], a[0], a[1], b[1], b[0] ; c[3] ;
; F ; LC85 ; reduce_or~2904, a[0], b[1], a[2], a[1], b[0], b[2] ; c[6] ;
; F ; LC83 ; b[0], a[0], b[1], a[2], b[2], a[1] ; reduce_or~2904 ;
; F ; LC90 ; reduce_or~2890, a[2], a[0], b[0], a[1], b[1], b[2] ; reduce_or~2861 ;
; F ; LC89 ; a[0], a[1], b[0], b[1] ; reduce_or~2892 ;
; F ; LC87 ; b[1], b[0], a[0], a[1], a[2], b[2] ; reduce_or~2855 ;
; G ; LC104 ; a[2], b[1], a[1], b[2], b[0], a[0] ; reduce_or~2824 ;
; G ; LC105 ; b[2], a[2], b[1], a[1], b[0], a[0] ; reduce_or~2824 ;
; G ; LC102 ; b[0], a[0], a[2], b[2], b[1], a[1] ; reduce_or~2837 ;
; G ; LC100 ; b[0], a[0], a[1], a[2], b[2], b[1] ; reduce_or~2831 ;
; G ; LC98 ; a[2], b[0], a[0], b[2] ; reduce_or~2810 ;
; G ; LC97 ; b[0], a[0], a[2], b[2], a[1], b[1], reduce_or~2801 ; c[5] ;
; G ; LC103 ; reduce_or~2879, b[0], a[0], a[1], a[2], b[2], b[1] ; reduce_or~2839 ;
; G ; LC101 ; reduce_or~2873, b[0], a[0], a[1], a[2], b[2], b[1] ; reduce_or~2839 ;
; G ; LC99 ; reduce_or~2869, reduce_or~2800, a[1], b[1], reduce_or~2801, a[2], b[2], reduce_or~2802, reduce_or~2803, b[0], a[0], reduce_or~2804 ; c[1] ;
; H ; LC118 ; ; en ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------+----------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Wed Oct 12 10:23:07 2005
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off add -c add
Info: Selected device EPM7128SLC84-15 for design "add"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Wed Oct 12 10:23:11 2005
Info: Elapsed time: 00:00:04
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -