grammar

將VHDL設計轉換成Verilog設計的程式

Translation grammar in YACC format

trad  : rem entity rem architecture rem
rem      : /* Empty */
         | remlist
remlist  : REM 
         | REM remlist
entity : ENTITY NAME IS PORT '(' rem portlist ')' ';' rem END NAME ';'
portlist  : s_list ':' dir type rem 
          | s_list ':' dir type ';' rem portlist
dir    : IN
       | OUT
type   : BIT 
       | BITVECT '('vec_range ')' {$$=$3;}
       | NAME 
vec_range : NATURAL updown NATURAL 
          | NATURAL
updown : DOWNTO
       | TO
architecture : ARCHITECTURE NAME OF NAME IS rem a_decl BEGN doindent
               a_body END NAME ';' unindent 
doindent : /* Empty */
unindent : /* Empty */
a_decl    : /* Empty */
          | a_decl SIGNAL s_list ':' type ';' rem
          | a_decl CONSTANT NAME ':' type ':' '=' STRING ';' rem 
          | a_decl TYPE NAME IS '(' s_list ')' ';' rem 
          | a_decl COMPONENT NAME PORT nolist '(' rem portlist ')' ';'
            rem END COMPONENT ';' yeslist rem 
nolist : /*Empty*/
yeslist : /*Empty*/
s_list : NAME 
       | NAME ',' s_list
a_body : rem
       | rem signal '<' '=' sigvalue doothers a_body 
       | rem WITH expr SELECT rem yeswith signal '<' '=' with_list
         doothers a_body
       | rem NAME ':' NAME PORT MAP '(' doindent map_list ')' ';'
         unindent a_body
       | optname PROCESS '(' sign_list ')' p_decl BEGN doindent
         p_body END PROCESS oname ';' unindent a_body
       | optname PROCESS '(' sign_list ')' p_decl BEGN doindent rem
         IF edge THEN p_body END IF ';' END PROCESS oname ';'
         unindent a_body
       | optname PROCESS '(' sign_list ')' p_decl BEGN doindent rem
         IF exprc THEN doindent p_body unindent ELSIF edge THEN doindent
         p_body unindent END IF ';' END PROCESS oname ';' unindent a_body
oname : /*Empty*/
      | NAME 
optname : rem
        | rem NAME ':'
edge : NAME '\'' EVENT AND exprc
     | exprc AND NAME '\'' EVENT
     | POSEDGE '(' NAME ')'
     | NEGEDGE '(' NAME ')'
yeswith : /*Empty*/
doothers : /*Empty*/
with_list : with_item ';'
          | with_item ',' rem with_list
          | expr delay WHEN OTHERS ';'
with_item : expr delay WHEN wlist
p_decl : rem
       | rem VARIABLE s_list ':' type ';' p_decl
p_body : rem
       | rem signal ':' '=' expr ';' doothers p_body
       | rem signal '<' '=' sigvalue doothers p_body
       | rem IF exprc THEN doindent p_body unindent elsepart END IF ';' p_body
       | rem CASE signal IS rem cases END CASE ';' p_body
       | rem NULLV ';' p_body
elsepart : /*Empty*/
         | ELSIF exprc THEN doindent p_body unindent elsepart
         | ELSE doindent p_body unindent
cases : WHEN wlist '=' '>' doindent p_body unindent cases
      | WHEN OTHERS '=' '>' doindent p_body unindent
wlist : wvalue
      | wlist '|' wvalue
wvalue : STRING
       | NAME
sign_list : signal
          | signal ',' sign_list
sigvalue : expr delay ';'
         | expr delay WHEN exprc ';'
         | expr delay WHEN exprc ELSE nodelay sigvalue
nodelay  : /* empty */
delay    : /* empty */
         | AFTER NATURAL UNIT
map_list : rem map_item
         | rem map_item ',' map_list
map_item : signal
         | NAME '=' '>' signal
signal : NAME
       | NAME '('vec_range ')'
expr : signal
     | STRING
     | '(' OTHERS '=' '>' STRING ')'
     | expr '&' expr
     | '-' expr %prec UMINUS
     | '+' expr %prec UPLUS
     | expr '+' expr
     | expr '-' expr
     | expr '*' expr
     | expr '/' expr
     | NOT expr
     | expr AND expr
     | expr OR expr
     | expr XOR expr
     | '(' expr ')'
exprc : conf
      | '(' exprc ')'
      | exprc AND exprc %prec ANDL
      | exprc OR exprc %prec ORL
      | NOT exprc %prec NOTL
conf : expr '=' expr %prec EQUAL
     | expr '>' expr
     | expr '>' '=' expr %prec BIGEQ
     | expr '<' expr
     | expr '<' '=' expr %prec LESSEQ 
     | expr '/' '=' expr %prec NOTEQ