div.tan.qmsg

div的verilog开发程序

{ "Info" "ITDB_TSU_RESULT" "touch:inst4\|q reset clk 0.586 ns register " "Info: tsu for register \"touch:inst4\|q\" (data pin = \"reset\", clock pin = \"clk\") is 0.586 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.503 ns + Longest pin register " "Info: + Longest pin to register delay is 3.503 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset 1 PIN PIN_28 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 5; PIN Node = 'reset'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 88 56 224 104 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.296 ns) + CELL(0.738 ns) 3.503 ns touch:inst4\|q 2 REG LC_X1_Y16_N4 2 " "Info: 2: + IC(1.296 ns) + CELL(0.738 ns) = 3.503 ns; Loc. = LC_X1_Y16_N4; Fanout = 2; REG Node = 'touch:inst4\|q'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "2.034 ns" { reset touch:inst4|q } "NODE_NAME" } } { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns ( 63.00 % ) " "Info: Total cell delay = 2.207 ns ( 63.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.296 ns ( 37.00 % ) " "Info: Total interconnect delay = 1.296 ns ( 37.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "3.503 ns" { reset touch:inst4|q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "3.503 ns" { reset reset~out0 touch:inst4|q } { 0.000ns 0.000ns 1.296ns } { 0.000ns 1.469ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 104 56 224 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns touch:inst4\|q 2 REG LC_X1_Y16_N4 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y16_N4; Fanout = 2; REG Node = 'touch:inst4\|q'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "1.485 ns" { clk touch:inst4|q } "NODE_NAME" } } { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk touch:inst4|q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 touch:inst4|q } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "3.503 ns" { reset touch:inst4|q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "3.503 ns" { reset reset~out0 touch:inst4|q } { 0.000ns 0.000ns 1.296ns } { 0.000ns 1.469ns 0.738ns } } } { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk touch:inst4|q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 touch:inst4|q } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q touch:inst4\|q 6.446 ns register " "Info: tco from clock \"clk\" to destination pin \"q\" through register \"touch:inst4\|q\" is 6.446 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 104 56 224 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns touch:inst4\|q 2 REG LC_X1_Y16_N4 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y16_N4; Fanout = 2; REG Node = 'touch:inst4\|q'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "1.485 ns" { clk touch:inst4|q } "NODE_NAME" } } { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk touch:inst4|q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 touch:inst4|q } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.268 ns + Longest register pin " "Info: + Longest register to pin delay is 3.268 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns touch:inst4\|q 1 REG LC_X1_Y16_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y16_N4; Fanout = 2; REG Node = 'touch:inst4\|q'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "" { touch:inst4|q } "NODE_NAME" } } { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.144 ns) + CELL(2.124 ns) 3.268 ns q 2 PIN PIN_15 0 " "Info: 2: + IC(1.144 ns) + CELL(2.124 ns) = 3.268 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'q'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "3.268 ns" { touch:inst4|q q } "NODE_NAME" } } { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 32 480 656 48 "q" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 64.99 % ) " "Info: Total cell delay = 2.124 ns ( 64.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.144 ns ( 35.01 % ) " "Info: Total interconnect delay = 1.144 ns ( 35.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "3.268 ns" { touch:inst4|q q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "3.268 ns" { touch:inst4|q q } { 0.000ns 1.144ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk touch:inst4|q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 touch:inst4|q } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "3.268 ns" { touch:inst4|q q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "3.268 ns" { touch:inst4|q q } { 0.000ns 1.144ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "touch:inst4\|q reset clk -0.534 ns register " "Info: th for register \"touch:inst4\|q\" (data pin = \"reset\", clock pin = \"clk\") is -0.534 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 104 56 224 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns touch:inst4\|q 2 REG LC_X1_Y16_N4 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y16_N4; Fanout = 2; REG Node = 'touch:inst4\|q'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "1.485 ns" { clk touch:inst4|q } "NODE_NAME" } } { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk touch:inst4|q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 touch:inst4|q } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.503 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.503 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset 1 PIN PIN_28 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 5; PIN Node = 'reset'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 88 56 224 104 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.296 ns) + CELL(0.738 ns) 3.503 ns touch:inst4\|q 2 REG LC_X1_Y16_N4 2 " "Info: 2: + IC(1.296 ns) + CELL(0.738 ns) = 3.503 ns; Loc. = LC_X1_Y16_N4; Fanout = 2; REG Node = 'touch:inst4\|q'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "2.034 ns" { reset touch:inst4|q } "NODE_NAME" } } { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns ( 63.00 % ) " "Info: Total cell delay = 2.207 ns ( 63.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.296 ns ( 37.00 % ) " "Info: Total interconnect delay = 1.296 ns ( 37.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "3.503 ns" { reset touch:inst4|q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "3.503 ns" { reset reset~out0 touch:inst4|q } { 0.000ns 0.000ns 1.296ns } { 0.000ns 1.469ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk touch:inst4|q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 touch:inst4|q } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "3.503 ns" { reset touch:inst4|q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "3.503 ns" { reset reset~out0 touch:inst4|q } { 0.000ns 0.000ns 1.296ns } { 0.000ns 1.469ns 0.738ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 15 16:27:05 2007 " "Info: Processing ended: Fri Jun 15 16:27:05 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}