div.tan.qmsg

div的verilog开发程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 15 16:27:04 2007 " "Info: Processing started: Fri Jun 15 16:27:04 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off div -c div --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div -c div --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 104 56 224 120 "clk" "" } } } } { "d:/q6.0/win/Assignment Editor.qase" "" { Assignment "d:/q6.0/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register touch:inst4\|a\[2\] touch:inst4\|q 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"touch:inst4\|a\[2\]\" and destination register \"touch:inst4\|q\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.462 ns + Longest register register " "Info: + Longest register to register delay is 1.462 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns touch:inst4\|a\[2\] 1 REG LC_X1_Y16_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y16_N5; Fanout = 3; REG Node = 'touch:inst4\|a\[2\]'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "" { touch:inst4|a[2] } "NODE_NAME" } } { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.442 ns) 0.971 ns touch:inst4\|q~63 2 COMB LC_X1_Y16_N3 1 " "Info: 2: + IC(0.529 ns) + CELL(0.442 ns) = 0.971 ns; Loc. = LC_X1_Y16_N3; Fanout = 1; COMB Node = 'touch:inst4\|q~63'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "0.971 ns" { touch:inst4|a[2] touch:inst4|q~63 } "NODE_NAME" } } { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 1.462 ns touch:inst4\|q 3 REG LC_X1_Y16_N4 2 " "Info: 3: + IC(0.182 ns) + CELL(0.309 ns) = 1.462 ns; Loc. = LC_X1_Y16_N4; Fanout = 2; REG Node = 'touch:inst4\|q'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "0.491 ns" { touch:inst4|q~63 touch:inst4|q } "NODE_NAME" } } { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.751 ns ( 51.37 % ) " "Info: Total cell delay = 0.751 ns ( 51.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.711 ns ( 48.63 % ) " "Info: Total interconnect delay = 0.711 ns ( 48.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "1.462 ns" { touch:inst4|a[2] touch:inst4|q~63 touch:inst4|q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "1.462 ns" { touch:inst4|a[2] touch:inst4|q~63 touch:inst4|q } { 0.000ns 0.529ns 0.182ns } { 0.000ns 0.442ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 104 56 224 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns touch:inst4\|q 2 REG LC_X1_Y16_N4 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y16_N4; Fanout = 2; REG Node = 'touch:inst4\|q'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "1.485 ns" { clk touch:inst4|q } "NODE_NAME" } } { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk touch:inst4|q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 touch:inst4|q } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div.bdf" "" { Schematic "F:/杨华/程序/div/div.bdf" { { 104 56 224 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns touch:inst4\|a\[2\] 2 REG LC_X1_Y16_N5 3 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y16_N5; Fanout = 3; REG Node = 'touch:inst4\|a\[2\]'" {  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "1.485 ns" { clk touch:inst4|a[2] } "NODE_NAME" } } { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk touch:inst4|a[2] } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 touch:inst4|a[2] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk touch:inst4|q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 touch:inst4|q } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk touch:inst4|a[2] } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 touch:inst4|a[2] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "1.462 ns" { touch:inst4|a[2] touch:inst4|q~63 touch:inst4|q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "1.462 ns" { touch:inst4|a[2] touch:inst4|q~63 touch:inst4|q } { 0.000ns 0.529ns 0.182ns } { 0.000ns 0.442ns 0.309ns } } } { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk touch:inst4|q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 touch:inst4|q } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "2.954 ns" { clk touch:inst4|a[2] } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 touch:inst4|a[2] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/q6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/q6.0/win/TimingClosureFloorplan.fld" "" "" { touch:inst4|q } "NODE_NAME" } } { "d:/q6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/q6.0/win/Technology_Viewer.qrui" "" { touch:inst4|q } {  } {  } } } { "touch.vhd" "" { Text "F:/杨华/程序/div/touch.vhd" 10 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}