div.tan.rpt

div的verilog开发程序

; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; touch:inst4|a[1] ; touch:inst4|a[2] ; clk        ; clk      ; None                        ; None                      ; 0.873 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; touch:inst4|a[1] ; touch:inst4|a[1] ; clk        ; clk      ; None                        ; None                      ; 0.872 ns                ;
+-------+------------------------------------------------+------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------+
; tsu                                                                  ;
+-------+--------------+------------+-------+---------------+----------+
; Slack ; Required tsu ; Actual tsu ; From  ; To            ; To Clock ;
+-------+--------------+------------+-------+---------------+----------+
; N/A   ; None         ; 0.586 ns   ; reset ; touch:inst4|q ; clk      ;
+-------+--------------+------------+-------+---------------+----------+


+---------------------------------------------------------------------+
; tco                                                                 ;
+-------+--------------+------------+---------------+----+------------+
; Slack ; Required tco ; Actual tco ; From          ; To ; From Clock ;
+-------+--------------+------------+---------------+----+------------+
; N/A   ; None         ; 6.446 ns   ; touch:inst4|q ; q  ; clk        ;
+-------+--------------+------------+---------------+----+------------+


+----------------------------------------------------------------------------+
; th                                                                         ;
+---------------+-------------+-----------+-------+---------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To            ; To Clock ;
+---------------+-------------+-----------+-------+---------------+----------+
; N/A           ; None        ; -0.534 ns ; reset ; touch:inst4|q ; clk      ;
+---------------+-------------+-----------+-------+---------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Jun 15 16:27:04 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div -c div --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "touch:inst4|a[2]" and destination register "touch:inst4|q"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.462 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y16_N5; Fanout = 3; REG Node = 'touch:inst4|a[2]'
            Info: 2: + IC(0.529 ns) + CELL(0.442 ns) = 0.971 ns; Loc. = LC_X1_Y16_N3; Fanout = 1; COMB Node = 'touch:inst4|q~63'
            Info: 3: + IC(0.182 ns) + CELL(0.309 ns) = 1.462 ns; Loc. = LC_X1_Y16_N4; Fanout = 2; REG Node = 'touch:inst4|q'
            Info: Total cell delay = 0.751 ns ( 51.37 % )
            Info: Total interconnect delay = 0.711 ns ( 48.63 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.954 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y16_N4; Fanout = 2; REG Node = 'touch:inst4|q'
                Info: Total cell delay = 2.180 ns ( 73.80 % )
                Info: Total interconnect delay = 0.774 ns ( 26.20 % )
            Info: - Longest clock path from clock "clk" to source register is 2.954 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y16_N5; Fanout = 3; REG Node = 'touch:inst4|a[2]'
                Info: Total cell delay = 2.180 ns ( 73.80 % )
                Info: Total interconnect delay = 0.774 ns ( 26.20 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "touch:inst4|q" (data pin = "reset", clock pin = "clk") is 0.586 ns
    Info: + Longest pin to register delay is 3.503 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 5; PIN Node = 'reset'
        Info: 2: + IC(1.296 ns) + CELL(0.738 ns) = 3.503 ns; Loc. = LC_X1_Y16_N4; Fanout = 2; REG Node = 'touch:inst4|q'
        Info: Total cell delay = 2.207 ns ( 63.00 % )
        Info: Total interconnect delay = 1.296 ns ( 37.00 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y16_N4; Fanout = 2; REG Node = 'touch:inst4|q'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
Info: tco from clock "clk" to destination pin "q" through register "touch:inst4|q" is 6.446 ns
    Info: + Longest clock path from clock "clk" to source register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y16_N4; Fanout = 2; REG Node = 'touch:inst4|q'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.268 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y16_N4; Fanout = 2; REG Node = 'touch:inst4|q'
        Info: 2: + IC(1.144 ns) + CELL(2.124 ns) = 3.268 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'q'
        Info: Total cell delay = 2.124 ns ( 64.99 % )
        Info: Total interconnect delay = 1.144 ns ( 35.01 % )
Info: th for register "touch:inst4|q" (data pin = "reset", clock pin = "clk") is -0.534 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y16_N4; Fanout = 2; REG Node = 'touch:inst4|q'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 3.503 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 5; PIN Node = 'reset'
        Info: 2: + IC(1.296 ns) + CELL(0.738 ns) = 3.503 ns; Loc. = LC_X1_Y16_N4; Fanout = 2; REG Node = 'touch:inst4|q'
        Info: Total cell delay = 2.207 ns ( 63.00 % )
        Info: Total interconnect delay = 1.296 ns ( 37.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Jun 15 16:27:05 2007
    Info: Elapsed time: 00:00:02