div1248.vhd

div的verilog开发程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity div1248 is 
         port (
              a    : in  std_logic_vector(3 downto 0);
              out1 : out std_logic;
              out2 : out std_logic;
              out4 : out std_logic;
              out8 : out std_logic);
end div1248;

architecture rtl of div1248 is
 
begin 

 process( a)
   begin
      out1<=a(0);
 end process; 

 process( a)
   begin
      out2<=a(1);
end process; 

process( a)
  begin
     out4<=a(2);
end process; 

process( a)
  begin
     out8<=a(3);
end process; 

end rtl;