freq.tan.qmsg

简易数字频率计

{ "Info" "ITDB_FULL_TCO_RESULT" "signal cout1\[5\] Lock:inst5\|cout\[1\] 12.850 ns register " "Info: tco from clock \"signal\" to destination pin \"cout1\[5\]\" through register \"Lock:inst5\|cout\[1\]\" is 12.850 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "signal source 7.332 ns + Longest register " "Info: + Longest clock path from clock \"signal\" to source register is 7.332 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns signal 1 CLK PIN_M21 25 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 25; CLK Node = 'signal'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { signal } "NODE_NAME" } } { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { { 264 16 184 280 "signal" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.688 ns) + CELL(0.698 ns) 3.111 ns Counter:inst1\|lock 2 REG LC_X8_Y11_N9 21 " "Info: 2: + IC(1.688 ns) + CELL(0.698 ns) = 3.111 ns; Loc. = LC_X8_Y11_N9; Fanout = 21; REG Node = 'Counter:inst1\|lock'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.386 ns" { signal Counter:inst1|lock } "NODE_NAME" } } { "Counter.v" "" { Text "E:/Freq/Counter.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.679 ns) + CELL(0.542 ns) 7.332 ns Lock:inst5\|cout\[1\] 3 REG LC_X7_Y11_N7 7 " "Info: 3: + IC(3.679 ns) + CELL(0.542 ns) = 7.332 ns; Loc. = LC_X7_Y11_N7; Fanout = 7; REG Node = 'Lock:inst5\|cout\[1\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.221 ns" { Counter:inst1|lock Lock:inst5|cout[1] } "NODE_NAME" } } { "Lock.v" "" { Text "E:/Freq/Lock.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.965 ns ( 26.80 % ) " "Info: Total cell delay = 1.965 ns ( 26.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.367 ns ( 73.20 % ) " "Info: Total interconnect delay = 5.367 ns ( 73.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.332 ns" { signal Counter:inst1|lock Lock:inst5|cout[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.332 ns" { signal signal~out0 Counter:inst1|lock Lock:inst5|cout[1] } { 0.000ns 0.000ns 1.688ns 3.679ns } { 0.000ns 0.725ns 0.698ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "Lock.v" "" { Text "E:/Freq/Lock.v" 11 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.362 ns + Longest register pin " "Info: + Longest register to pin delay is 5.362 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Lock:inst5\|cout\[1\] 1 REG LC_X7_Y11_N7 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y11_N7; Fanout = 7; REG Node = 'Lock:inst5\|cout\[1\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Lock:inst5|cout[1] } "NODE_NAME" } } { "Lock.v" "" { Text "E:/Freq/Lock.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.366 ns) 0.816 ns Display:inst11\|Decoder0~56 2 COMB LC_X7_Y11_N1 1 " "Info: 2: + IC(0.450 ns) + CELL(0.366 ns) = 0.816 ns; Loc. = LC_X7_Y11_N1; Fanout = 1; COMB Node = 'Display:inst11\|Decoder0~56'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.816 ns" { Lock:inst5|cout[1] Display:inst11|Decoder0~56 } "NODE_NAME" } } { "Display.v" "" { Text "E:/Freq/Display.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.142 ns) + CELL(2.404 ns) 5.362 ns cout1\[5\] 3 PIN PIN_A17 0 " "Info: 3: + IC(2.142 ns) + CELL(2.404 ns) = 5.362 ns; Loc. = PIN_A17; Fanout = 0; PIN Node = 'cout1\[5\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.546 ns" { Display:inst11|Decoder0~56 cout1[5] } "NODE_NAME" } } { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { { 192 1144 1320 208 "cout1\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.770 ns ( 51.66 % ) " "Info: Total cell delay = 2.770 ns ( 51.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.592 ns ( 48.34 % ) " "Info: Total interconnect delay = 2.592 ns ( 48.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.362 ns" { Lock:inst5|cout[1] Display:inst11|Decoder0~56 cout1[5] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.362 ns" { Lock:inst5|cout[1] Display:inst11|Decoder0~56 cout1[5] } { 0.000ns 0.450ns 2.142ns } { 0.000ns 0.366ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.332 ns" { signal Counter:inst1|lock Lock:inst5|cout[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.332 ns" { signal signal~out0 Counter:inst1|lock Lock:inst5|cout[1] } { 0.000ns 0.000ns 1.688ns 3.679ns } { 0.000ns 0.725ns 0.698ns 0.542ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.362 ns" { Lock:inst5|cout[1] Display:inst11|Decoder0~56 cout1[5] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.362 ns" { Lock:inst5|cout[1] Display:inst11|Decoder0~56 cout1[5] } { 0.000ns 0.450ns 2.142ns } { 0.000ns 0.366ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 23 16:33:22 2007 " "Info: Processing ended: Sun Sep 23 16:33:22 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}