counter.v

来自「简易数字频率计」· Verilog 代码 · 共 41 行

//计数模块
module Counter(reset,signal,en,cntover,cntlow,lock,cout1,cout2,cout3,cout4);
input signal,en;//en为分频器输出的方波信号
output cntover,cntlow,lock,reset;
output [3:0]cout1,cout2,cout3,cout4;
reg cntover,cntlow,lock;
reg [3:0]cout1,cout2,cout3,cout4;
wire reset;

assign reset=(cntover||cntlow||lock);

always@(posedge signal)

begin
if(reset)
begin cout1<=0;cout2<=0;cout3<=0;cout4<=0;cntlow<=0;cntover<=0;end
else if(en)
begin
if((cout1==9)&&(cout2!=9)) begin cout1<=0;cout2<=cout2+1;cntover<=0;cntlow<=0;end
else if((cout1==9)&&(cout2==9)&&(cout3!=9)) begin cout1<=0;cout2<=0;cout3<=cout3+1;cntlow<=0;end
else if((cout1==9)&&(cout2==9)&&(cout3==9)&&(cout4!=9)) begin cout1<=0;cout2<=0;cout3<=0;cout4<=cout4+1;end
else if((cout1==9)&&(cout2==9)&&(cout3==9)&&(cout4==9)) begin cntover<=1; end
else begin cout1<=cout1+1; cntover<=0;end

end
else begin cntover<=0;cntlow<=0;end
//end


//always@(negedge en)
//begin
if(!en)
begin
if((cout4==0)&&(cout3<=9)&&(cout2<=9)&&(cout1<=9)) begin cntlow<=1;lock<=0;end
else if(cntover) begin lock<=0;cntlow<=0;end
else begin lock<=1;cntlow<=0; end
if((cout4==0)&&(cout3==0)&&(cout2==0)&&(cout1==0)) begin cntlow<=0;cntover<=0;lock<=0;end
end
end

endmodule