freq.tan.qmsg

简易数字频率计

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register DivFreq:inst2\|num\[8\] register DivFreq:inst2\|num\[17\] 147.73 MHz 6.769 ns Internal " "Info: Clock \"clk\" has Internal fmax of 147.73 MHz between source register \"DivFreq:inst2\|num\[8\]\" and destination register \"DivFreq:inst2\|num\[17\]\" (period= 6.769 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.592 ns + Longest register register " "Info: + Longest register to register delay is 6.592 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DivFreq:inst2\|num\[8\] 1 REG LC_X34_Y10_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y10_N1; Fanout = 4; REG Node = 'DivFreq:inst2\|num\[8\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DivFreq:inst2|num[8] } "NODE_NAME" } } { "DivFreq.v" "" { Text "E:/Freq/DivFreq.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.109 ns) + CELL(0.183 ns) 1.292 ns DivFreq:inst2\|Equal0~184 2 COMB LC_X35_Y11_N5 1 " "Info: 2: + IC(1.109 ns) + CELL(0.183 ns) = 1.292 ns; Loc. = LC_X35_Y11_N5; Fanout = 1; COMB Node = 'DivFreq:inst2\|Equal0~184'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.292 ns" { DivFreq:inst2|num[8] DivFreq:inst2|Equal0~184 } "NODE_NAME" } } { "DivFreq.v" "" { Text "E:/Freq/DivFreq.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.071 ns) + CELL(0.075 ns) 2.438 ns DivFreq:inst2\|Equal0~188 3 COMB LC_X34_Y9_N8 2 " "Info: 3: + IC(1.071 ns) + CELL(0.075 ns) = 2.438 ns; Loc. = LC_X34_Y9_N8; Fanout = 2; COMB Node = 'DivFreq:inst2\|Equal0~188'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.146 ns" { DivFreq:inst2|Equal0~184 DivFreq:inst2|Equal0~188 } "NODE_NAME" } } { "DivFreq.v" "" { Text "E:/Freq/DivFreq.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.075 ns) 2.647 ns DivFreq:inst2\|Equal1~122 4 COMB LC_X34_Y9_N9 2 " "Info: 4: + IC(0.134 ns) + CELL(0.075 ns) = 2.647 ns; Loc. = LC_X34_Y9_N9; Fanout = 2; COMB Node = 'DivFreq:inst2\|Equal1~122'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.209 ns" { DivFreq:inst2|Equal0~188 DivFreq:inst2|Equal1~122 } "NODE_NAME" } } { "DivFreq.v" "" { Text "E:/Freq/DivFreq.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.075 ns) 3.753 ns DivFreq:inst2\|Equal1~124 5 COMB LC_X33_Y11_N3 2 " "Info: 5: + IC(1.031 ns) + CELL(0.075 ns) = 3.753 ns; Loc. = LC_X33_Y11_N3; Fanout = 2; COMB Node = 'DivFreq:inst2\|Equal1~124'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.106 ns" { DivFreq:inst2|Equal1~122 DivFreq:inst2|Equal1~124 } "NODE_NAME" } } { "DivFreq.v" "" { Text "E:/Freq/DivFreq.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.494 ns) + CELL(0.183 ns) 4.430 ns DivFreq:inst2\|num\[3\]~509 6 COMB LC_X34_Y11_N2 1 " "Info: 6: + IC(0.494 ns) + CELL(0.183 ns) = 4.430 ns; Loc. = LC_X34_Y11_N2; Fanout = 1; COMB Node = 'DivFreq:inst2\|num\[3\]~509'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.677 ns" { DivFreq:inst2|Equal1~124 DivFreq:inst2|num[3]~509 } "NODE_NAME" } } { "DivFreq.v" "" { Text "E:/Freq/DivFreq.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.322 ns) + CELL(0.075 ns) 4.827 ns DivFreq:inst2\|num\[3\]~510 7 COMB LC_X34_Y11_N0 24 " "Info: 7: + IC(0.322 ns) + CELL(0.075 ns) = 4.827 ns; Loc. = LC_X34_Y11_N0; Fanout = 24; COMB Node = 'DivFreq:inst2\|num\[3\]~510'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.397 ns" { DivFreq:inst2|num[3]~509 DivFreq:inst2|num[3]~510 } "NODE_NAME" } } { "DivFreq.v" "" { Text "E:/Freq/DivFreq.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.004 ns) + CELL(0.761 ns) 6.592 ns DivFreq:inst2\|num\[17\] 8 REG LC_X34_Y9_N0 4 " "Info: 8: + IC(1.004 ns) + CELL(0.761 ns) = 6.592 ns; Loc. = LC_X34_Y9_N0; Fanout = 4; REG Node = 'DivFreq:inst2\|num\[17\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.765 ns" { DivFreq:inst2|num[3]~510 DivFreq:inst2|num[17] } "NODE_NAME" } } { "DivFreq.v" "" { Text "E:/Freq/DivFreq.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.427 ns ( 21.65 % ) " "Info: Total cell delay = 1.427 ns ( 21.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.165 ns ( 78.35 % ) " "Info: Total interconnect delay = 5.165 ns ( 78.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.592 ns" { DivFreq:inst2|num[8] DivFreq:inst2|Equal0~184 DivFreq:inst2|Equal0~188 DivFreq:inst2|Equal1~122 DivFreq:inst2|Equal1~124 DivFreq:inst2|num[3]~509 DivFreq:inst2|num[3]~510 DivFreq:inst2|num[17] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.592 ns" { DivFreq:inst2|num[8] DivFreq:inst2|Equal0~184 DivFreq:inst2|Equal0~188 DivFreq:inst2|Equal1~122 DivFreq:inst2|Equal1~124 DivFreq:inst2|num[3]~509 DivFreq:inst2|num[3]~510 DivFreq:inst2|num[17] } { 0.000ns 1.109ns 1.071ns 0.134ns 1.031ns 0.494ns 0.322ns 1.004ns } { 0.000ns 0.183ns 0.075ns 0.075ns 0.075ns 0.183ns 0.075ns 0.761ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.011 ns - Smallest " "Info: - Smallest clock skew is -0.011 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.967 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.967 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 25 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { { 72 -248 -80 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.597 ns) + CELL(0.542 ns) 2.967 ns DivFreq:inst2\|num\[17\] 2 REG LC_X34_Y9_N0 4 " "Info: 2: + IC(1.597 ns) + CELL(0.542 ns) = 2.967 ns; Loc. = LC_X34_Y9_N0; Fanout = 4; REG Node = 'DivFreq:inst2\|num\[17\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.139 ns" { clk DivFreq:inst2|num[17] } "NODE_NAME" } } { "DivFreq.v" "" { Text "E:/Freq/DivFreq.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.17 % ) " "Info: Total cell delay = 1.370 ns ( 46.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.597 ns ( 53.83 % ) " "Info: Total interconnect delay = 1.597 ns ( 53.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.967 ns" { clk DivFreq:inst2|num[17] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.967 ns" { clk clk~out0 DivFreq:inst2|num[17] } { 0.000ns 0.000ns 1.597ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.978 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.978 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 25 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { { 72 -248 -80 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.608 ns) + CELL(0.542 ns) 2.978 ns DivFreq:inst2\|num\[8\] 2 REG LC_X34_Y10_N1 4 " "Info: 2: + IC(1.608 ns) + CELL(0.542 ns) = 2.978 ns; Loc. = LC_X34_Y10_N1; Fanout = 4; REG Node = 'DivFreq:inst2\|num\[8\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.150 ns" { clk DivFreq:inst2|num[8] } "NODE_NAME" } } { "DivFreq.v" "" { Text "E:/Freq/DivFreq.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.00 % ) " "Info: Total cell delay = 1.370 ns ( 46.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.608 ns ( 54.00 % ) " "Info: Total interconnect delay = 1.608 ns ( 54.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.978 ns" { clk DivFreq:inst2|num[8] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.978 ns" { clk clk~out0 DivFreq:inst2|num[8] } { 0.000ns 0.000ns 1.608ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.967 ns" { clk DivFreq:inst2|num[17] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.967 ns" { clk clk~out0 DivFreq:inst2|num[17] } { 0.000ns 0.000ns 1.597ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.978 ns" { clk DivFreq:inst2|num[8] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.978 ns" { clk clk~out0 DivFreq:inst2|num[8] } { 0.000ns 0.000ns 1.608ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "DivFreq.v" "" { Text "E:/Freq/DivFreq.v" 59 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "DivFreq.v" "" { Text "E:/Freq/DivFreq.v" 59 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.592 ns" { DivFreq:inst2|num[8] DivFreq:inst2|Equal0~184 DivFreq:inst2|Equal0~188 DivFreq:inst2|Equal1~122 DivFreq:inst2|Equal1~124 DivFreq:inst2|num[3]~509 DivFreq:inst2|num[3]~510 DivFreq:inst2|num[17] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.592 ns" { DivFreq:inst2|num[8] DivFreq:inst2|Equal0~184 DivFreq:inst2|Equal0~188 DivFreq:inst2|Equal1~122 DivFreq:inst2|Equal1~124 DivFreq:inst2|num[3]~509 DivFreq:inst2|num[3]~510 DivFreq:inst2|num[17] } { 0.000ns 1.109ns 1.071ns 0.134ns 1.031ns 0.494ns 0.322ns 1.004ns } { 0.000ns 0.183ns 0.075ns 0.075ns 0.075ns 0.183ns 0.075ns 0.761ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.967 ns" { clk DivFreq:inst2|num[17] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.967 ns" { clk clk~out0 DivFreq:inst2|num[17] } { 0.000ns 0.000ns 1.597ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.978 ns" { clk DivFreq:inst2|num[8] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.978 ns" { clk clk~out0 DivFreq:inst2|num[8] } { 0.000ns 0.000ns 1.608ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "signal 16 " "Warning: Circuit may not operate. Detected 16 non-operational path(s) clocked by clock \"signal\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "Counter:inst1\|cout1\[1\] Lock:inst5\|cout\[1\] signal 3.419 ns " "Info: Found hold time violation between source  pin or register \"Counter:inst1\|cout1\[1\]\" and destination pin or register \"Lock:inst5\|cout\[1\]\" for clock \"signal\" (Hold time is 3.419 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.377 ns + Largest " "Info: + Largest clock skew is 4.377 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "signal destination 7.332 ns + Longest register " "Info: + Longest clock path from clock \"signal\" to destination register is 7.332 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns signal 1 CLK PIN_M21 25 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 25; CLK Node = 'signal'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { signal } "NODE_NAME" } } { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { { 264 16 184 280 "signal" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.688 ns) + CELL(0.698 ns) 3.111 ns Counter:inst1\|lock 2 REG LC_X8_Y11_N9 21 " "Info: 2: + IC(1.688 ns) + CELL(0.698 ns) = 3.111 ns; Loc. = LC_X8_Y11_N9; Fanout = 21; REG Node = 'Counter:inst1\|lock'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.386 ns" { signal Counter:inst1|lock } "NODE_NAME" } } { "Counter.v" "" { Text "E:/Freq/Counter.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.679 ns) + CELL(0.542 ns) 7.332 ns Lock:inst5\|cout\[1\] 3 REG LC_X7_Y11_N7 7 " "Info: 3: + IC(3.679 ns) + CELL(0.542 ns) = 7.332 ns; Loc. = LC_X7_Y11_N7; Fanout = 7; REG Node = 'Lock:inst5\|cout\[1\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.221 ns" { Counter:inst1|lock Lock:inst5|cout[1] } "NODE_NAME" } } { "Lock.v" "" { Text "E:/Freq/Lock.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.965 ns ( 26.80 % ) " "Info: Total cell delay = 1.965 ns ( 26.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.367 ns ( 73.20 % ) " "Info: Total interconnect delay = 5.367 ns ( 73.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.332 ns" { signal Counter:inst1|lock Lock:inst5|cout[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.332 ns" { signal signal~out0 Counter:inst1|lock Lock:inst5|cout[1] } { 0.000ns 0.000ns 1.688ns 3.679ns } { 0.000ns 0.725ns 0.698ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "signal source 2.955 ns - Shortest register " "Info: - Shortest clock path from clock \"signal\" to source register is 2.955 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns signal 1 CLK PIN_M21 25 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 25; CLK Node = 'signal'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { signal } "NODE_NAME" } } { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { { 264 16 184 280 "signal" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.688 ns) + CELL(0.542 ns) 2.955 ns Counter:inst1\|cout1\[1\] 2 REG LC_X9_Y11_N7 7 " "Info: 2: + IC(1.688 ns) + CELL(0.542 ns) = 2.955 ns; Loc. = LC_X9_Y11_N7; Fanout = 7; REG Node = 'Counter:inst1\|cout1\[1\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.230 ns" { signal Counter:inst1|cout1[1] } "NODE_NAME" } } { "Counter.v" "" { Text "E:/Freq/Counter.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 42.88 % ) " "Info: Total cell delay = 1.267 ns ( 42.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.688 ns ( 57.12 % ) " "Info: Total interconnect delay = 1.688 ns ( 57.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.955 ns" { signal Counter:inst1|cout1[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.955 ns" { signal signal~out0 Counter:inst1|cout1[1] } { 0.000ns 0.000ns 1.688ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.332 ns" { signal Counter:inst1|lock Lock:inst5|cout[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.332 ns" { signal signal~out0 Counter:inst1|lock Lock:inst5|cout[1] } { 0.000ns 0.000ns 1.688ns 3.679ns } { 0.000ns 0.725ns 0.698ns 0.542ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.955 ns" { signal Counter:inst1|cout1[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.955 ns" { signal signal~out0 Counter:inst1|cout1[1] } { 0.000ns 0.000ns 1.688ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns - " "Info: - Micro clock to output delay of source is 0.156 ns" {  } { { "Counter.v" "" { Text "E:/Freq/Counter.v" 39 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.902 ns - Shortest register register " "Info: - Shortest register to register delay is 0.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Counter:inst1\|cout1\[1\] 1 REG LC_X9_Y11_N7 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y11_N7; Fanout = 7; REG Node = 'Counter:inst1\|cout1\[1\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Counter:inst1|cout1[1] } "NODE_NAME" } } { "Counter.v" "" { Text "E:/Freq/Counter.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.817 ns) + CELL(0.085 ns) 0.902 ns Lock:inst5\|cout\[1\] 2 REG LC_X7_Y11_N7 7 " "Info: 2: + IC(0.817 ns) + CELL(0.085 ns) = 0.902 ns; Loc. = LC_X7_Y11_N7; Fanout = 7; REG Node = 'Lock:inst5\|cout\[1\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.902 ns" { Counter:inst1|cout1[1] Lock:inst5|cout[1] } "NODE_NAME" } } { "Lock.v" "" { Text "E:/Freq/Lock.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.085 ns ( 9.42 % ) " "Info: Total cell delay = 0.085 ns ( 9.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.817 ns ( 90.58 % ) " "Info: Total interconnect delay = 0.817 ns ( 90.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.902 ns" { Counter:inst1|cout1[1] Lock:inst5|cout[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "0.902 ns" { Counter:inst1|cout1[1] Lock:inst5|cout[1] } { 0.000ns 0.817ns } { 0.000ns 0.085ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "Lock.v" "" { Text "E:/Freq/Lock.v" 11 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.332 ns" { signal Counter:inst1|lock Lock:inst5|cout[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.332 ns" { signal signal~out0 Counter:inst1|lock Lock:inst5|cout[1] } { 0.000ns 0.000ns 1.688ns 3.679ns } { 0.000ns 0.725ns 0.698ns 0.542ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.955 ns" { signal Counter:inst1|cout1[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.955 ns" { signal signal~out0 Counter:inst1|cout1[1] } { 0.000ns 0.000ns 1.688ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.902 ns" { Counter:inst1|cout1[1] Lock:inst5|cout[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "0.902 ns" { Counter:inst1|cout1[1] Lock:inst5|cout[1] } { 0.000ns 0.817ns } { 0.000ns 0.085ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}