freq.tan.qmsg

简易数字频率计

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "signal " "Info: Assuming node \"signal\" is an undefined clock" {  } { { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { { 264 16 184 280 "signal" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "signal" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { { 72 -248 -80 88 "clk" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Counter:inst1\|lock " "Info: Detected ripple clock \"Counter:inst1\|lock\" as buffer" {  } { { "Counter.v" "" { Text "E:/Freq/Counter.v" 4 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Counter:inst1\|lock" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "signal register Counter:inst1\|lock register Counter:inst1\|cout1\[0\] 279.96 MHz 3.572 ns Internal " "Info: Clock \"signal\" has Internal fmax of 279.96 MHz between source register \"Counter:inst1\|lock\" and destination register \"Counter:inst1\|cout1\[0\]\" (period= 3.572 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.406 ns + Longest register register " "Info: + Longest register to register delay is 3.406 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Counter:inst1\|lock 1 REG LC_X8_Y11_N9 21 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y11_N9; Fanout = 21; REG Node = 'Counter:inst1\|lock'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Counter:inst1|lock } "NODE_NAME" } } { "Counter.v" "" { Text "E:/Freq/Counter.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.183 ns) 1.183 ns Counter:inst1\|reset 2 COMB LC_X13_Y11_N8 12 " "Info: 2: + IC(1.000 ns) + CELL(0.183 ns) = 1.183 ns; Loc. = LC_X13_Y11_N8; Fanout = 12; COMB Node = 'Counter:inst1\|reset'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.183 ns" { Counter:inst1|lock Counter:inst1|reset } "NODE_NAME" } } { "Counter.v" "" { Text "E:/Freq/Counter.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.338 ns) + CELL(0.366 ns) 1.887 ns Counter:inst1\|cout1\[0\]~265 3 COMB LC_X13_Y11_N2 5 " "Info: 3: + IC(0.338 ns) + CELL(0.366 ns) = 1.887 ns; Loc. = LC_X13_Y11_N2; Fanout = 5; COMB Node = 'Counter:inst1\|cout1\[0\]~265'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.704 ns" { Counter:inst1|reset Counter:inst1|cout1[0]~265 } "NODE_NAME" } } { "Counter.v" "" { Text "E:/Freq/Counter.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.758 ns) + CELL(0.761 ns) 3.406 ns Counter:inst1\|cout1\[0\] 4 REG LC_X9_Y11_N6 7 " "Info: 4: + IC(0.758 ns) + CELL(0.761 ns) = 3.406 ns; Loc. = LC_X9_Y11_N6; Fanout = 7; REG Node = 'Counter:inst1\|cout1\[0\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.519 ns" { Counter:inst1|cout1[0]~265 Counter:inst1|cout1[0] } "NODE_NAME" } } { "Counter.v" "" { Text "E:/Freq/Counter.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.310 ns ( 38.46 % ) " "Info: Total cell delay = 1.310 ns ( 38.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.096 ns ( 61.54 % ) " "Info: Total interconnect delay = 2.096 ns ( 61.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.406 ns" { Counter:inst1|lock Counter:inst1|reset Counter:inst1|cout1[0]~265 Counter:inst1|cout1[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.406 ns" { Counter:inst1|lock Counter:inst1|reset Counter:inst1|cout1[0]~265 Counter:inst1|cout1[0] } { 0.000ns 1.000ns 0.338ns 0.758ns } { 0.000ns 0.183ns 0.366ns 0.761ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "signal destination 2.955 ns + Shortest register " "Info: + Shortest clock path from clock \"signal\" to destination register is 2.955 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns signal 1 CLK PIN_M21 25 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 25; CLK Node = 'signal'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { signal } "NODE_NAME" } } { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { { 264 16 184 280 "signal" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.688 ns) + CELL(0.542 ns) 2.955 ns Counter:inst1\|cout1\[0\] 2 REG LC_X9_Y11_N6 7 " "Info: 2: + IC(1.688 ns) + CELL(0.542 ns) = 2.955 ns; Loc. = LC_X9_Y11_N6; Fanout = 7; REG Node = 'Counter:inst1\|cout1\[0\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.230 ns" { signal Counter:inst1|cout1[0] } "NODE_NAME" } } { "Counter.v" "" { Text "E:/Freq/Counter.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 42.88 % ) " "Info: Total cell delay = 1.267 ns ( 42.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.688 ns ( 57.12 % ) " "Info: Total interconnect delay = 1.688 ns ( 57.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.955 ns" { signal Counter:inst1|cout1[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.955 ns" { signal signal~out0 Counter:inst1|cout1[0] } { 0.000ns 0.000ns 1.688ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "signal source 2.955 ns - Longest register " "Info: - Longest clock path from clock \"signal\" to source register is 2.955 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns signal 1 CLK PIN_M21 25 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 25; CLK Node = 'signal'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { signal } "NODE_NAME" } } { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { { 264 16 184 280 "signal" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.688 ns) + CELL(0.542 ns) 2.955 ns Counter:inst1\|lock 2 REG LC_X8_Y11_N9 21 " "Info: 2: + IC(1.688 ns) + CELL(0.542 ns) = 2.955 ns; Loc. = LC_X8_Y11_N9; Fanout = 21; REG Node = 'Counter:inst1\|lock'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.230 ns" { signal Counter:inst1|lock } "NODE_NAME" } } { "Counter.v" "" { Text "E:/Freq/Counter.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 42.88 % ) " "Info: Total cell delay = 1.267 ns ( 42.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.688 ns ( 57.12 % ) " "Info: Total interconnect delay = 1.688 ns ( 57.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.955 ns" { signal Counter:inst1|lock } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.955 ns" { signal signal~out0 Counter:inst1|lock } { 0.000ns 0.000ns 1.688ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.955 ns" { signal Counter:inst1|cout1[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.955 ns" { signal signal~out0 Counter:inst1|cout1[0] } { 0.000ns 0.000ns 1.688ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.955 ns" { signal Counter:inst1|lock } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.955 ns" { signal signal~out0 Counter:inst1|lock } { 0.000ns 0.000ns 1.688ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "Counter.v" "" { Text "E:/Freq/Counter.v" 4 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "Counter.v" "" { Text "E:/Freq/Counter.v" 39 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.406 ns" { Counter:inst1|lock Counter:inst1|reset Counter:inst1|cout1[0]~265 Counter:inst1|cout1[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.406 ns" { Counter:inst1|lock Counter:inst1|reset Counter:inst1|cout1[0]~265 Counter:inst1|cout1[0] } { 0.000ns 1.000ns 0.338ns 0.758ns } { 0.000ns 0.183ns 0.366ns 0.761ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.955 ns" { signal Counter:inst1|cout1[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.955 ns" { signal signal~out0 Counter:inst1|cout1[0] } { 0.000ns 0.000ns 1.688ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.955 ns" { signal Counter:inst1|lock } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.955 ns" { signal signal~out0 Counter:inst1|lock } { 0.000ns 0.000ns 1.688ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}