freq.map.qmsg

简易数字频率计

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DivFreq DivFreq:inst2 " "Info: Elaborating entity \"DivFreq\" for hierarchy \"DivFreq:inst2\"" {  } { { "Freq.bdf" "inst2" { Schematic "E:/Freq/Freq.bdf" { { 48 72 232 144 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 DivFreq.v(23) " "Warning (10230): Verilog HDL assignment warning at DivFreq.v(23): truncated value with size 32 to match size of target (24)" {  } { { "DivFreq.v" "" { Text "E:/Freq/DivFreq.v" 23 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 DivFreq.v(32) " "Warning (10230): Verilog HDL assignment warning at DivFreq.v(32): truncated value with size 32 to match size of target (24)" {  } { { "DivFreq.v" "" { Text "E:/Freq/DivFreq.v" 32 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 DivFreq.v(41) " "Warning (10230): Verilog HDL assignment warning at DivFreq.v(41): truncated value with size 32 to match size of target (24)" {  } { { "DivFreq.v" "" { Text "E:/Freq/DivFreq.v" 41 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 DivFreq.v(50) " "Warning (10230): Verilog HDL assignment warning at DivFreq.v(50): truncated value with size 32 to match size of target (24)" {  } { { "DivFreq.v" "" { Text "E:/Freq/DivFreq.v" 50 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "Display.v(20) " "Warning (10273): Verilog HDL warning at Display.v(20): extended using \"x\" or \"z\"" {  } { { "Display.v" "" { Text "E:/Freq/Display.v" 20 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Warning" "WSGN_SEARCH_FILE" "Display.v 1 1 " "Warning: Using design file Display.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Display " "Info: Found entity 1: Display" {  } { { "Display.v" "" { Text "E:/Freq/Display.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Display Display:inst11 " "Info: Elaborating entity \"Display\" for hierarchy \"Display:inst11\"" {  } { { "Freq.bdf" "inst11" { Schematic "E:/Freq/Freq.bdf" { { 168 1000 1144 264 "inst11" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Lock.v 1 1 " "Warning: Using design file Lock.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Lock " "Info: Found entity 1: Lock" {  } { { "Lock.v" "" { Text "E:/Freq/Lock.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Lock Lock:inst5 " "Info: Elaborating entity \"Lock\" for hierarchy \"Lock:inst5\"" {  } { { "Freq.bdf" "inst5" { Schematic "E:/Freq/Freq.bdf" { { 168 680 824 264 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|Freq\|Control:inst\|present 6 " "Info: State machine \"\|Freq\|Control:inst\|present\" contains 6 states" {  } { { "Control.v" "" { Text "E:/Freq/Control.v" 18 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|Freq\|Control:inst\|present " "Info: Selected Auto state machine encoding method for state machine \"\|Freq\|Control:inst\|present\"" {  } { { "Control.v" "" { Text "E:/Freq/Control.v" 18 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|Freq\|Control:inst\|present " "Info: Encoding result for state machine \"\|Freq\|Control:inst\|present\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "6 " "Info: Completed encoding using 6 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control:inst\|present.flk_cnt " "Info: Encoded state bit \"Control:inst\|present.flk_cnt\"" {  } { { "Control.v" "" { Text "E:/Freq/Control.v" 18 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control:inst\|present.start_flk " "Info: Encoded state bit \"Control:inst\|present.start_flk\"" {  } { { "Control.v" "" { Text "E:/Freq/Control.v" 18 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control:inst\|present.fl0k_cnt " "Info: Encoded state bit \"Control:inst\|present.fl0k_cnt\"" {  } { { "Control.v" "" { Text "E:/Freq/Control.v" 18 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control:inst\|present.start_fl0k " "Info: Encoded state bit \"Control:inst\|present.start_fl0k\"" {  } { { "Control.v" "" { Text "E:/Freq/Control.v" 18 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control:inst\|present.fl00k_cnt " "Info: Encoded state bit \"Control:inst\|present.fl00k_cnt\"" {  } { { "Control.v" "" { Text "E:/Freq/Control.v" 18 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Control:inst\|present.start_fl00k " "Info: Encoded state bit \"Control:inst\|present.start_fl00k\"" {  } { { "Control.v" "" { Text "E:/Freq/Control.v" 18 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Freq\|Control:inst\|present.start_fl0k 000000 " "Info: State \"\|Freq\|Control:inst\|present.start_fl0k\" uses code string \"000000\"" {  } { { "Control.v" "" { Text "E:/Freq/Control.v" 18 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Freq\|Control:inst\|present.start_flk 010100 " "Info: State \"\|Freq\|Control:inst\|present.start_flk\" uses code string \"010100\"" {  } { { "Control.v" "" { Text "E:/Freq/Control.v" 18 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Freq\|Control:inst\|present.fl0k_cnt 001100 " "Info: State \"\|Freq\|Control:inst\|present.fl0k_cnt\" uses code string \"001100\"" {  } { { "Control.v" "" { Text "E:/Freq/Control.v" 18 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Freq\|Control:inst\|present.fl00k_cnt 000110 " "Info: State \"\|Freq\|Control:inst\|present.fl00k_cnt\" uses code string \"000110\"" {  } { { "Control.v" "" { Text "E:/Freq/Control.v" 18 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Freq\|Control:inst\|present.start_fl00k 000101 " "Info: State \"\|Freq\|Control:inst\|present.start_fl00k\" uses code string \"000101\"" {  } { { "Control.v" "" { Text "E:/Freq/Control.v" 18 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Freq\|Control:inst\|present.flk_cnt 100100 " "Info: State \"\|Freq\|Control:inst\|present.flk_cnt\" uses code string \"100100\"" {  } { { "Control.v" "" { Text "E:/Freq/Control.v" 18 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "Control.v" "" { Text "E:/Freq/Control.v" 18 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "cout1\[0\] VCC " "Warning: Pin \"cout1\[0\]\" stuck at VCC" {  } { { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { { 192 1144 1320 208 "cout1\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cout2\[0\] VCC " "Warning: Pin \"cout2\[0\]\" stuck at VCC" {  } { { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { { 296 1144 1320 312 "cout2\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cout3\[0\] VCC " "Warning: Pin \"cout3\[0\]\" stuck at VCC" {  } { { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { { 392 1144 1320 408 "cout3\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cout4\[0\] VCC " "Warning: Pin \"cout4\[0\]\" stuck at VCC" {  } { { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { { 504 1144 1320 520 "cout4\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "205 " "Info: Implemented 205 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "56 " "Info: Implemented 56 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "146 " "Info: Implemented 146 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 22 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 22 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 23 16:33:02 2007 " "Info: Processing ended: Sun Sep 23 16:33:02 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/Freq/Freq.map.smsg " "Info: Generated suppressed messages file E:/Freq/Freq.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}