freq.map.qmsg

简易数字频率计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 23 16:33:00 2007 " "Info: Processing started: Sun Sep 23 16:33:00 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Freq -c Freq " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Freq -c Freq" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Freq.bdf 1 1 " "Warning: Using design file Freq.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Freq " "Info: Found entity 1: Freq" {  } { { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Freq " "Info: Elaborating entity \"Freq\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "Display inst12 " "Warning: Block or symbol \"Display\" of instance \"inst12\" overlaps another block or symbol" {  } { { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { { 272 1000 1144 368 "inst12" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "Lock inst4 " "Warning: Block or symbol \"Lock\" of instance \"inst4\" overlaps another block or symbol" {  } { { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { { 272 680 824 368 "inst4" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "Lock inst5 " "Warning: Block or symbol \"Lock\" of instance \"inst5\" overlaps another block or symbol" {  } { { "Freq.bdf" "" { Schematic "E:/Freq/Freq.bdf" { { 168 680 824 264 "inst5" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "Control.v(66) " "Warning (10268): Verilog HDL information at Control.v(66): Always Construct contains both blocking and non-blocking assignments" {  } { { "Control.v" "" { Text "E:/Freq/Control.v" 66 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Warning" "WSGN_SEARCH_FILE" "Control.v 1 1 " "Warning: Using design file Control.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Control " "Info: Found entity 1: Control" {  } { { "Control.v" "" { Text "E:/Freq/Control.v" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Control Control:inst " "Info: Elaborating entity \"Control\" for hierarchy \"Control:inst\"" {  } { { "Freq.bdf" "inst" { Schematic "E:/Freq/Freq.bdf" { { 16 368 528 144 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Counter.v 1 1 " "Warning: Using design file Counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Counter " "Info: Found entity 1: Counter" {  } { { "Counter.v" "" { Text "E:/Freq/Counter.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Counter Counter:inst1 " "Info: Elaborating entity \"Counter\" for hierarchy \"Counter:inst1\"" {  } { { "Freq.bdf" "inst1" { Schematic "E:/Freq/Freq.bdf" { { 224 312 448 416 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 Counter.v(19) " "Warning (10230): Verilog HDL assignment warning at Counter.v(19): truncated value with size 32 to match size of target (4)" {  } { { "Counter.v" "" { Text "E:/Freq/Counter.v" 19 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 Counter.v(20) " "Warning (10230): Verilog HDL assignment warning at Counter.v(20): truncated value with size 32 to match size of target (4)" {  } { { "Counter.v" "" { Text "E:/Freq/Counter.v" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 Counter.v(21) " "Warning (10230): Verilog HDL assignment warning at Counter.v(21): truncated value with size 32 to match size of target (4)" {  } { { "Counter.v" "" { Text "E:/Freq/Counter.v" 21 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 Counter.v(23) " "Warning (10230): Verilog HDL assignment warning at Counter.v(23): truncated value with size 32 to match size of target (4)" {  } { { "Counter.v" "" { Text "E:/Freq/Counter.v" 23 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "DivFreq.v 1 1 " "Warning: Using design file DivFreq.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 DivFreq " "Info: Found entity 1: DivFreq" {  } { { "DivFreq.v" "" { Text "E:/Freq/DivFreq.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}