divfreq.v

来自「简易数字频率计」· Verilog 代码 · 共 61 行

module DivFreq(clk,reset,select,count_clk);
output count_clk;
input clk,reset;
input [1:0] select;
reg count_clk;
reg [23:0] num;

//always @ (posedge clk)
    
    //begin    if(reset)  count_clr<=1; 
  //     else count_clr<=0;
    //end
  
always @ (posedge clk )

   begin if(!reset) 
   case(select)
   2'b00: begin  
           if(num==499)   begin
	                       count_clk<=~count_clk;
                           num<=0;
                          end
            else num<=num+1;
                      
                
          end
   2'b01: begin if(num==4999) 
                 begin
	                       count_clk<=~count_clk;
                           num<=0;
                          end
            else num<=num+1;
                      
                
          end
   2'b11: begin if(num==49999) 
                 begin
	                       count_clk<=~count_clk;
                           num<=0;
                          end
            else num<=num+1;
                      
                
          end
   default: begin if(num==4999) 
                 begin
	                       count_clk<=~count_clk;
                           num<=0;
                          end
            else num<=num+1;
                      
                
          end
   endcase
 else   begin num<=0;
              count_clk<=1;
       end     

 end

endmodule