📄 freq.map.rpt
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; Total registers ; 66 ;
; Total logic cells in carry chains ; 32 ;
; I/O pins ; 59 ;
; Maximum fan-out node ; signal ;
; Maximum fan-out ; 25 ;
; Total fan-out ; 603 ;
; Average fan-out ; 2.94 ;
+---------------------------------------------+--------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+
; |Freq ; 146 (0) ; 66 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 59 ; 0 ; 80 (0) ; 16 (0) ; 50 (0) ; 32 (0) ; 0 (0) ; |Freq ;
; |Control:inst| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |Freq|Control:inst ;
; |Counter:inst1| ; 48 (48) ; 19 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 29 (29) ; 0 (0) ; 19 (19) ; 8 (8) ; 0 (0) ; |Freq|Counter:inst1 ;
; |Display:inst11| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |Freq|Display:inst11 ;
; |Display:inst12| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |Freq|Display:inst12 ;
; |Display:inst13| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |Freq|Display:inst13 ;
; |Display:inst14| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |Freq|Display:inst14 ;
; |DivFreq:inst2| ; 45 (45) ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (20) ; 0 (0) ; 25 (25) ; 24 (24) ; 0 (0) ; |Freq|DivFreq:inst2 ;
; |Lock:inst4| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |Freq|Lock:inst4 ;
; |Lock:inst5| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |Freq|Lock:inst5 ;
; |Lock:inst6| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |Freq|Lock:inst6 ;
; |Lock:inst7| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |Freq|Lock:inst7 ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |Freq|Control:inst|present ;
+---------------------+-----------------+-------------------+------------------+--------------------+-------------------+---------------------+
; Name ; present.flk_cnt ; present.start_flk ; present.fl0k_cnt ; present.start_fl0k ; present.fl00k_cnt ; present.start_fl00k ;
+---------------------+-----------------+-------------------+------------------+--------------------+-------------------+---------------------+
; present.start_fl0k ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; present.start_flk ; 0 ; 1 ; 0 ; 1 ; 0 ; 0 ;
; present.fl0k_cnt ; 0 ; 0 ; 1 ; 1 ; 0 ; 0 ;
; present.fl00k_cnt ; 0 ; 0 ; 0 ; 1 ; 1 ; 0 ;
; present.start_fl00k ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; present.flk_cnt ; 1 ; 0 ; 0 ; 1 ; 0 ; 0 ;
+---------------------+-----------------+-------------------+------------------+--------------------+-------------------+---------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 66 ;
; Number of registers using Synchronous Clear ; 32 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 6 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 12 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; 5:1 ; 4 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |Freq|Counter:inst1|cout4[3] ;
; 6:1 ; 4 bits ; 16 LEs ; 4 LEs ; 12 LEs ; Yes ; |Freq|Counter:inst1|cout2[3] ;
; 6:1 ; 4 bits ; 16 LEs ; 4 LEs ; 12 LEs ; Yes ; |Freq|Counter:inst1|cout3[0] ;
; 6:1 ; 4 bits ; 16 LEs ; 4 LEs ; 12 LEs ; Yes ; |Freq|Counter:inst1|cout1[0] ;
; 7:1 ; 24 bits ; 96 LEs ; 24 LEs ; 72 LEs ; Yes ; |Freq|DivFreq:inst2|num[3] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
+-----------------------------------------------------------+
; Parameter Settings for User Entity Instance: Control:inst ;
+----------------+--------+---------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+--------+---------------------------------+
; start_fl00k ; 000001 ; Binary ;
; fl00k_cnt ; 000010 ; Binary ;
; start_fl0k ; 000100 ; Binary ;
; fl0k_cnt ; 001000 ; Binary ;
; start_flk ; 010000 ; Binary ;
; flk_cnt ; 100000 ; Binary ;
+----------------+--------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sun Sep 23 16:33:00 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Freq -c Freq
Warning: Using design file Freq.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: Freq
Info: Elaborating entity "Freq" for the top level hierarchy
Warning: Block or symbol "Display" of instance "inst12" overlaps another block or symbol
Warning: Block or symbol "Lock" of instance "inst4" overlaps another block or symbol
Warning: Block or symbol "Lock" of instance "inst5" overlaps another block or symbol
Warning: Using design file Control.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: Control
Info: Elaborating entity "Control" for hierarchy "Control:inst"
Warning: Using design file Counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: Counter
Info: Elaborating entity "Counter" for hierarchy "Counter:inst1"
Warning (10230): Verilog HDL assignment warning at Counter.v(19): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at Counter.v(20): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at Counter.v(21): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at Counter.v(23): truncated value with size 32 to match size of target (4)
Warning: Using design file DivFreq.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: DivFreq
Info: Elaborating entity "DivFreq" for hierarchy "DivFreq:inst2"
Warning (10230): Verilog HDL assignment warning at DivFreq.v(23): truncated value with size 32 to match size of target (24)
Warning (10230): Verilog HDL assignment warning at DivFreq.v(32): truncated value with size 32 to match size of target (24)
Warning (10230): Verilog HDL assignment warning at DivFreq.v(41): truncated value with size 32 to match size of target (24)
Warning (10230): Verilog HDL assignment warning at DivFreq.v(50): truncated value with size 32 to match size of target (24)
Warning: Using design file Display.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: Display
Info: Elaborating entity "Display" for hierarchy "Display:inst11"
Warning: Using design file Lock.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: Lock
Info: Elaborating entity "Lock" for hierarchy "Lock:inst5"
Info: State machine "|Freq|Control:inst|present" contains 6 states
Info: Selected Auto state machine encoding method for state machine "|Freq|Control:inst|present"
Info: Encoding result for state machine "|Freq|Control:inst|present"
Info: Completed encoding using 6 state bits
Info: Encoded state bit "Control:inst|present.flk_cnt"
Info: Encoded state bit "Control:inst|present.start_flk"
Info: Encoded state bit "Control:inst|present.fl0k_cnt"
Info: Encoded state bit "Control:inst|present.start_fl0k"
Info: Encoded state bit "Control:inst|present.fl00k_cnt"
Info: Encoded state bit "Control:inst|present.start_fl00k"
Info: State "|Freq|Control:inst|present.start_fl0k" uses code string "000000"
Info: State "|Freq|Control:inst|present.start_flk" uses code string "010100"
Info: State "|Freq|Control:inst|present.fl0k_cnt" uses code string "001100"
Info: State "|Freq|Control:inst|present.fl00k_cnt" uses code string "000110"
Info: State "|Freq|Control:inst|present.start_fl00k" uses code string "000101"
Info: State "|Freq|Control:inst|present.flk_cnt" uses code string "100100"
Warning: Output pins are stuck at VCC or GND
Warning: Pin "cout1[0]" stuck at VCC
Warning: Pin "cout2[0]" stuck at VCC
Warning: Pin "cout3[0]" stuck at VCC
Warning: Pin "cout4[0]" stuck at VCC
Info: Implemented 205 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 56 output pins
Info: Implemented 146 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 22 warnings
Info: Processing ended: Sun Sep 23 16:33:02 2007
Info: Elapsed time: 00:00:03
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/Freq/Freq.map.smsg.
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