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📄 control.v

📁 简易数字频率计
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//控制模块
/*信号定义:
clk: 输入时钟;
clear: 为整个频率计的异步复位信号;
reset: 用来在量程转换开始时复位计数器;
std_f_sel: 用来选择标准时基;
cntover: 代表超量程;
cntlow: 代表欠量程;
lock:  向锁存器发出的锁存信号。
状态A,B,C,D,E,F 采用一位热码编码 */
module Control(std_f_sel,reset,clk,clear,cntover,cntlow,light_1k,light_10k,light_100k);
output[1:0] std_f_sel;
output reset;
output light_1k,light_10k,light_100k;
input clk,clear,cntover,cntlow;
reg[1:0] std_f_sel;
reg reset;
reg[5:0] present,next;
reg light_1k,light_10k,light_100k;
parameter start_fl00k=6'b000001,	
  	  fl00k_cnt=6'b000010,
  	  start_fl0k=6'b000100,
  	  fl0k_cnt=6'b001000,
  	  start_flk=6'b010000,
  	  flk_cnt=6'b100000;

always @(posedge clk or posedge clear)
begin
	if(clear) 	present<=start_fl0k;
	else 		present<=next;
end

always @(present or cntover or cntlow)
begin
case(present)
start_fl00k:		next<=fl00k_cnt;
fl00k_cnt:
	begin
	if(cntlow) 	next<=start_fl0k;
	else 		next<=fl00k_cnt;
	end
start_fl0k:		next<=fl0k_cnt;
fl0k_cnt:
	begin
	if(cntlow) 	next<=start_flk;
	else  if(cntover)  	next<=start_fl00k;
	else  		next<=fl0k_cnt;
	end
start_flk:		next<=flk_cnt;
flk_cnt:
	begin
	if(cntover) 	next<=start_fl0k;
	else  		next<=flk_cnt;
	end
default:		next<=start_fl0k;
endcase
end

/*always @(cntover or cntlow )  //符合量程时输出lock信号
begin
    if((!cntover)&&(!cntlow)) lock=1;
    else  lock<=0;
end*/


always @(present)
begin
case(present)
start_fl00k:	
begin	reset=1;  std_f_sel=2'b00;  
light_1k<=0;  light_10k<=0;  light_100k<=1;
end

fl00k_cnt:	
begin	reset=0;  std_f_sel=2'b00;  
light_1k<=0;  light_10k<=0;  light_100k<=1;
end

start_fl0k:	
begin	reset=1;  std_f_sel=2'b01;  
light_1k<=0;  light_10k<=1;  light_100k<=0;
end

fl0k_cnt:	
begin	reset=0;  std_f_sel=2'b01;  
light_1k<=0;  light_10k<=1;  light_100k<=0;
end

start_flk:	
begin 	reset=1;  std_f_sel=2'b11;  
light_1k<=1;  light_10k<=0;  light_100k<=0;
end

flk_cnt:	
begin	reset=0;  std_f_sel=2'b11;  
light_1k<=1;  light_10k<=0;  light_100k<=0;
end

default:	
begin	reset=1;  std_f_sel=2'b01;  
light_1k<=0;  light_10k<=1;  light_100k<=0;
end
endcase
end
endmodule

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