display.v

来自「简易数字频率计」· Verilog 代码 · 共 24 行

//显示模块
module Display(cin,cout);
input [3:0]cin;
output [7:0]cout;
reg [7:0]cout;

always@(cin)
begin
case(cin)
8'd0: cout=8'b00000011;
8'd1: cout=8'b10011111;
8'd2: cout=8'b00100101;
8'd3: cout=8'b00001101;
8'd4: cout=8'b10011001;
8'd5: cout=8'b01001001;
8'd6: cout=8'b01000001;
8'd7: cout=8'b00011111;
8'd8: cout=8'b00000001;
8'd9: cout=8'b00001001;
default:cout=8'bx;
endcase
end
endmodule