📄 state.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity state is
port( CLK33 : in std_logic ;
RSTB : in std_logic ;
STS : in std_logic ;
CMP : in std_logic ;
DATA_OUT : in std_logic_vector(7 downto 0) ;
C_OEN : in std_logic ;
EN_FLASH : in std_logic ;
EN_APEX : in std_logic ;
EN_LAST : in std_logic ;
EN_VERIFY : in std_logic ;
CONF_END : in std_logic ;
CONF_ADD : in std_logic_vector(21 downto 0);
INIT_EN : in std_logic ;
C_ERR : in std_logic ;
VERI_ERR : in std_logic ;
CNT3V_C : in std_logic ;
CHECK_ST : out std_logic ;
READ_ST : out std_logic ;
INIT_ST : out std_logic ;
CONF_ST : out std_logic ;
VERI_ST : out std_logic ;
FLASH_RUN : out std_logic ;
ERASE_RUN : out std_logic ;
RD_P : out std_logic ;
VERI_ACK : out std_logic ;
DA : out std_logic_vector(7 downto 0);
ADD : out std_logic_vector(21 downto 0);
CEN : out std_logic ;
WEN : out std_logic ;
OEN : out std_logic
);
end;
architecture rtl of state is
---------------------------------------------------------------
constant D_A5H :std_logic_vector(7 downto 0):= "10100101" ;
constant D_20H :std_logic_vector(7 downto 0):= "00100000" ;
constant D_40H :std_logic_vector(7 downto 0):= "01000000" ;
constant D_D0H :std_logic_vector(7 downto 0):= "11010000" ;
constant D_FFH :std_logic_vector(7 downto 0):= "11111111" ;
constant A_000001H :std_logic_vector(21 downto 0):= "0000000000000000000001" ;
constant A_000000H :std_logic_vector(21 downto 0):= "0000000000000000000000" ;
---------------------------------------------------------------
constant START : std_logic_vector(4 downto 0):= "00001" ;
constant CHECK : std_logic_vector(4 downto 0):= "00010" ;
------------------------------------------------------------
constant CONF_SET : std_logic_vector(4 downto 0):= "00011" ;
constant CONF : std_logic_vector(4 downto 0):= "00100" ;
------------------------------------------------------------
constant DEL1ST : std_logic_vector(4 downto 0):= "01000" ;
constant DEL2ND : std_logic_vector(4 downto 0):= "01001" ;
constant DEL : std_logic_vector(4 downto 0):= "01010" ;
------------------------------------------------------------
constant PRO1ST : std_logic_vector(4 downto 0):= "10000" ;
constant PRO2ND : std_logic_vector(4 downto 0):= "10001" ;
constant PRO : std_logic_vector(4 downto 0):= "10010" ;
constant READ_SET : std_logic_vector(4 downto 0):= "10011" ;
constant READ : std_logic_vector(4 downto 0):= "10100" ;
------------------------------------------------------------
constant INIT : std_logic_vector(4 downto 0):= "00000" ;
------------------------------------------------------------
constant VERI_SET : std_logic_vector(4 downto 0):= "00101" ;
constant VERIFY : std_logic_vector(4 downto 0):= "00110" ;
------------------------------------------------------------
signal CURRENT_STATE : std_logic_vector(4 downto 0) ;
signal NEXT_STATE : std_logic_vector(4 downto 0) ;
signal NEXT_ST : std_logic ;
signal CTEN3 : std_logic ;
signal CNT3 : std_logic_vector(2 downto 0) ;
signal CNT3_C : std_logic ;
signal CNT3_E : std_logic ;
signal W_EN : std_logic ;
signal O_EN : std_logic ;
signal CNT3_4 : std_logic ;
signal CNT22 : std_logic_vector(21 downto 0) ;
signal CNT22_E : std_logic ;
signal CNT5 : std_logic_vector(4 downto 0) ;
signal CNT5_E : std_logic ;
signal BA_END : std_logic ;
signal BADD : std_logic_vector(21 downto 0) ;
signal STS1S : std_logic ;
signal STS2S : std_logic ;
signal END_P : std_logic ;
signal ENB_S : std_logic ;
signal ENB_R : std_logic ;
signal ENB : std_logic ;
signal WRUN : std_logic ;
signal ERUN : std_logic ;
signal VERI_OEN : std_logic ;
signal VERI_OEN_1S : std_logic ;
signal VERI_OEN_2S : std_logic ;
signal VERI_OEN_3S : std_logic ;
signal VERI_OEN_4S : std_logic ;
signal VERI_NS : std_logic ;
signal ENB_S_V : std_logic ;
signal ENB_R_V : std_logic ;
begin
-- 3bit counter -----------------------------------------------------------------------------------
CNT3_E <= ((CTEN3) or (INIT_EN)) ;
process (CLK33,RSTB) begin
if (RSTB='0') then
CNT3 <= "000" ;
elsif (CLK33' event and CLK33='1') then
if (CNT3_E='1') then
CNT3 <= CNT3 + '1' ;
end if ;
end if ;
end process ;
CNT3_C <= '1' when CNT3="111" else '0' ;
CNT3_4 <= '1' when CNT3="100" else '0' ;
RD_P <= CNT3_4 when ((CURRENT_STATE = READ) or (CURRENT_STATE = CHECK)) else '0' ;
process (CNT3) begin
case CNT3 is
when "000" => W_EN <= '1' ;
when "001" => W_EN <= '1' ;
when "010" => W_EN <= '1' ;
when "011" => W_EN <= '0' ;
when "100" => W_EN <= '0' ;
when "101" => W_EN <= '0' ;
when "110" => W_EN <= '1' ;
when "111" => W_EN <= '1' ;
when others => W_EN <= '1' ;
end case ;
end process ;
process (CNT3) begin
case CNT3 is
when "000" => O_EN <= '1' ;
when "001" => O_EN <= '1' ;
when "010" => O_EN <= '0' ;
when "011" => O_EN <= '0' ;
when "100" => O_EN <= '0' ;
when "101" => O_EN <= '0' ;
when "110" => O_EN <= '1' ;
when "111" => O_EN <= '1' ;
when others => O_EN <= '1' ;
end case ;
end process ;
-- 22bit address Counter --------------------------------------------------------------------------
CNT22_E <= '1' when ((CNT3_C='1') and (EN_LAST='0') and (VERI_ERR='0') and (CURRENT_STATE = READ)) else '0' ;
process (CLK33,RSTB) begin
if (RSTB='0') then
CNT22 <= A_000001H ;
elsif (CLK33' event and CLK33='1') then
if (ENB = '0') then
CNT22 <= A_000001H ;
elsif (CNT22_E='1' or CNT3V_C='1') then
CNT22 <= CNT22 + '1' ;
end if ;
end if ;
end process ;
VERI_OEN <= '0' when ((CURRENT_STATE = VERIFY) and (CNT22 /= A_000000H )) else '1' ;
-- 4bit Shift regster -----------------------------------------------------------------------------
process (CLK33,RSTB) begin
if (RSTB='0') then
VERI_OEN_1S <= '0' ;
VERI_OEN_2S <= '0' ;
VERI_OEN_3S <= '0' ;
VERI_OEN_4S <= '0' ;
elsif (CLK33' event and CLK33='1') then
VERI_OEN_1S <= not(VERI_OEN) ;
VERI_OEN_2S <= VERI_OEN_1S ;
VERI_OEN_3S <= VERI_OEN_2S ;
VERI_OEN_4S <= VERI_OEN_3S ;
end if ;
end process ;
VERI_NS <= not(VERI_OEN_3S) and VERI_OEN_4S ;
VERI_ACK <= VERI_OEN_4S ;
-- 5bit counter -----------------------------------------------------------------------------------
CNT5_E <= END_P when (CURRENT_STATE = DEL) else '0' ;
process (CLK33,RSTB) begin
if (RSTB='0') then
CNT5 <= "00000" ;
elsif (CLK33' event and CLK33='1') then
if (CNT5_E='1') then
CNT5 <= CNT5 + '1' ;
end if ;
end if ;
end process ;
BA_END <= '1' when CNT5="11111" else '0' ;
BADD <= CNT5 & "00000000000000000" ;
-- STS posedge bibun pulse ------------------------------------------------------------------------
process (CLK33,RSTB) begin
if (RSTB='0') then
STS1S <= '1' ;
STS2S <= '1' ;
elsif (CLK33' event and CLK33='1') then
STS1S <= STS ;
STS2S <= STS1S ;
end if ;
end process ;
END_P <= (STS1S) and not(STS2S) ;
-- ENABLE CREATE ----------------------------------------------------------------------------------
ENB_S <= '1' when ((END_P='1') and (BA_END='1')) else '0' ;
ENB_R <= '1' when ((NEXT_ST='1') and (CURRENT_STATE = READ) and ((EN_LAST='1') or (VERI_ERR='1'))) else '0' ;
ENB_S_V <= '1' when ((CNT3_C='1') and (CURRENT_STATE = VERI_SET)) else '0' ;
ENB_R_V <= '1' when ((VERI_NS='1') and (CURRENT_STATE = VERIFY)) else '0' ;
process (CLK33,RSTB) begin
if (RSTB='0') then
ENB <= '0' ;
elsif (CLK33' event and CLK33='1') then
if (ENB_S='1' or ENB_S_V='1') then
ENB <= '1';
elsif (ENB_R='1' or ENB_R_V='1')then
ENB <= '0';
end if;
end if;
end process ;
-- state machine ----------------------------------------------------------------------------------
NEXT_ST <= ((CNT3_C) or (END_P) or (CONF_END) or (C_ERR) or (VERI_NS)) ;
process (CLK33,RSTB) begin
if (RSTB='0') then
CURRENT_STATE <= START ;
elsif (CLK33' event and CLK33='1') then
if (NEXT_ST='1') then
CURRENT_STATE <= NEXT_STATE ;
end if;
end if;
end process ;
process (CURRENT_STATE,CMP,EN_FLASH,EN_APEX,EN_LAST,EN_VERIFY,W_EN,O_EN,C_OEN,VERI_OEN ,
CONF_ADD,ENB,BADD,CNT22,DATA_OUT,BA_END) begin
case CURRENT_STATE is
when START =>
ADD <= (others => '0') ;
DA <= D_FFH ;
WEN <= W_EN ;
CEN <= '0' ;
OEN <= '1' ;
CTEN3 <= '1' ;
NEXT_STATE <= CHECK ;
when CHECK =>
ADD <= (others => '0') ;
DA <= (others => '0') ;
WEN <= '1' ;
CEN <= '0' ;
OEN <= O_EN ;
CTEN3 <= '1' ;
if ((CMP='1') and (EN_APEX='1'))then
NEXT_STATE <= CONF ;
else
NEXT_STATE <= INIT ;
end if ;
when INIT =>
ADD <= (others => '0') ;
DA <= (others => '0') ;
WEN <= '1' ;
CEN <= '1' ;
OEN <= '1' ;
CTEN3 <= '0' ;
if ((ENB='0') and (EN_FLASH='1')) then
NEXT_STATE <= DEL1ST ;
elsif (ENB='1') then
NEXT_STATE <= PRO1ST ;
elsif (EN_APEX='1') then
NEXT_STATE <= CONF_SET ;
elsif (EN_VERIFY='1') then
NEXT_STATE <= VERI_SET ;
else
NEXT_STATE <= INIT ;
end if ;
when DEL1ST =>
ADD <= BADD ;
DA <= D_20H ;
WEN <= W_EN ;
CEN <= '0' ;
OEN <= '1' ;
CTEN3 <= '1' ;
NEXT_STATE <= DEL2ND ;
when DEL2ND =>
ADD <= BADD ;
DA <= D_D0H ;
WEN <= W_EN ;
CEN <= '0' ;
OEN <= '1' ;
CTEN3 <= '1' ;
NEXT_STATE <= DEL ;
when DEL =>
ADD <= BADD ;
DA <= (others => '0') ;
WEN <= '1' ;
CEN <= '1' ;
OEN <= '1' ;
CTEN3 <= '0' ;
if (BA_END='0') then
NEXT_STATE <= DEL1ST ;
else
NEXT_STATE <= PRO1ST ;
end if ;
when PRO1ST =>
if (EN_LAST='1') then
ADD <= (others => '0') ;
else
ADD <= CNT22 ;
end if ;
DA <= D_40H ;
WEN <= W_EN ;
CEN <= '0' ;
OEN <= '1' ;
CTEN3 <= '1' ;
NEXT_STATE <= PRO2ND ;
when PRO2ND =>
if (EN_LAST='1') then
ADD <= (others => '0') ;
DA <= D_A5H ; --1/11 D_01H -> D_A5H
else
ADD <= CNT22 ;
DA <= DATA_OUT ;
end if ;
WEN <= W_EN ;
CEN <= '0' ;
OEN <= '1' ;
CTEN3 <= '1' ;
NEXT_STATE <= PRO ;
when PRO =>
if (EN_LAST='1') then
ADD <= (others => '0') ;
DA <= D_A5H ; --1/11 D_01H -> D_A5H
else
ADD <= CNT22 ;
DA <= DATA_OUT ;
end if ;
WEN <= '1' ;
CEN <= '1' ;
OEN <= '1' ;
CTEN3 <= '0' ;
NEXT_STATE <= READ_SET ;
when READ_SET =>
if (EN_LAST='1') then
ADD <= (others => '0') ;
else
ADD <= CNT22 ;
end if ;
DA <= D_FFH ;
WEN <= W_EN ;
CEN <= '0' ;
OEN <= '1' ;
CTEN3 <= '1' ;
NEXT_STATE <= READ ;
when READ =>
if (EN_LAST='1') then
ADD <= (others => '0') ;
else
ADD <= CNT22 ;
end if ;
DA <= (others => '0') ;
WEN <= '1' ;
CEN <= '0' ; -- 1/11 '1'-> '0'
OEN <= O_EN ;
CTEN3 <= '1' ;
NEXT_STATE <= INIT ;
when CONF_SET =>
ADD <= (others => '0') ;
DA <= D_FFH ;
WEN <= W_EN ;
CEN <= '0' ;
OEN <= '1' ;
CTEN3 <= '1' ;
NEXT_STATE <= CONF ;
when CONF =>
ADD <= CONF_ADD ;
DA <= (others => '0') ;
WEN <= '1';
CEN <= C_OEN ;
OEN <= C_OEN ;
CTEN3 <= '0' ;
NEXT_STATE <= INIT ;
when VERI_SET =>
ADD <= (others => '0') ;
DA <= D_FFH ;
WEN <= W_EN ;
CEN <= '0' ;
OEN <= '1' ;
CTEN3 <= '1' ;
NEXT_STATE <= VERIFY ;
when VERIFY =>
ADD <= CNT22 ;
DA <= (others => '0') ;
WEN <= '1' ;
CEN <= '0' ;
OEN <= VERI_OEN ;
CTEN3 <= '0' ;
NEXT_STATE <= INIT ;
when others =>
ADD <= (others => '0');
DA <= (others => '0') ;
WEN <= '1';
CEN <= '1' ;
OEN <= '1';
CTEN3 <= '0' ;
NEXT_STATE <= INIT ;
end case ;
end process ;
CHECK_ST <= '1' when (CURRENT_STATE = CHECK) else '0' ;
READ_ST <= '1' when (CURRENT_STATE = READ) else '0' ;
CONF_ST <= '1' when (CURRENT_STATE = CONF) else '0' ;
INIT_ST <= '1' when (CURRENT_STATE = INIT) else '0' ;
VERI_ST <= '1' when (CURRENT_STATE = VERIFY) else '0' ;
WRUN <= CURRENT_STATE(4) ;
ERUN <= CURRENT_STATE(3) ;
FLASH_RUN <= WRUN ;
ERASE_RUN <= ERUN ;
---------------------------------------------------------------------------------------------------
end rtl;
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