flashloader.vhd

intel flash控制器VHDL 源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity flashloader is
	  port( CLK33	    : in std_logic; 			  --CLOCK(32MHz)
		RSTB	    : in std_logic;			  --RESET('L'Active)
		DATA_MODE   : in std_logic; 			  --PC interface
		DATA_PC	    : in std_logic; 			  --PC interface
		STB	    : in std_logic; 			  --PC interface
		NSTATUS	    : in std_logic; 			  --APEX interface
		CONF_DONE   : in std_logic; 			  --APEX interface
		STS	    : in std_logic; 			  --flash memory interface
		DA	    : inout std_logic_vector(7 downto 0); --flash memory interface
		ADD	    : out std_logic_vector(21 downto 0);  --flash memory interface
		WEN         : out std_logic ;			  --flash memory interface
		CEN 	    : out std_logic ;                     --flash memory interface
		OEN	    : out std_logic ;                     --flash memory interface
		ACK	    : out std_logic ;			  --PC interface
		CONF_STATUS : out std_logic ;                     --PC interface
		NCONFIG     : out std_logic ;			  --APEX interface
		DATA0       : out std_logic ;			  --APEX interface
		DCLK	    : out std_logic ;                     --APEX interface(DCLK=32MHz)
		ERASE_RUN   : out std_logic ;			  --LED interface(1:ON 0:OFF)
		CONF_RUN    : out std_logic ;                     --LED interface(1:ON 0:OFF)
		CONF_ERR    : out std_logic ;                     --LED interface(1:ON 0:OFF)
		FLASH_RUN   : out std_logic ;                     --LED interface(1:ON 0:OFF)
		FLASH_ERR   : out std_logic                       --LED interface(1:ON 0:OFF)
	      );
end;

architecture rtl of flashloader is
---------------------------------------------------------------------------------------------------
component pcif
	port( DATA_MODE : in std_logic ;
	      DATA_PC	: in std_logic ;
	      STB	: in std_logic ;
	      CLK33	: in std_logic ;
	      RSTB	: in std_logic ;
	      INIT_ST	: in std_logic ;
	      VERI_ST   : in std_logic ;
	      VERI_ACK  : in std_logic ;
 	      EN_FLASH  : out std_logic ;
	      EN_APEX	: out std_logic ;
	      EN_LAST	: out std_logic ;
	      EN_VERIFY : out std_logic ;
  	      DATA_OUT  : out std_logic_vector(7 downto 0) ;
	      INIT_EN	: out std_logic ;
	      MODE_U    : out std_logic ;
	      STB_UP    : out std_logic ;
	      CNT3V_C   : out std_logic ;
	      COUNT     : out std_logic_vector(2 downto 0) ;
	      ACK	: out std_logic
	     );
end component;

component state
	port( CLK33	: in std_logic ;
	      RSTB	: in std_logic ;
              STS	: in std_logic ;
	      CMP	: in std_logic ;
	      DATA_OUT	: in std_logic_vector(7 downto 0) ;
	      C_OEN	: in std_logic ;
	      EN_FLASH	: in std_logic ;
	      EN_APEX	: in std_logic ;
	      EN_LAST	: in std_logic ;
	      EN_VERIFY : in std_logic ;
	      CONF_END	: in std_logic ;
	      CONF_ADD	: in std_logic_vector(21 downto 0);
	      INIT_EN	: in std_logic ;
	      C_ERR	: in std_logic ;
	      VERI_ERR	: in std_logic ;
	      CNT3V_C   : in std_logic ;
	      CHECK_ST  : out std_logic ;
	      READ_ST   : out std_logic ;
	      INIT_ST	: out std_logic ;
	      CONF_ST	: out std_logic ;
	      VERI_ST   : out std_logic ;
	      FLASH_RUN	: out std_logic ;
	      ERASE_RUN	: out std_logic ;
	      RD_P	: out std_logic ;
	      VERI_ACK  : out std_logic ;
	      DA	: out std_logic_vector(7 downto 0);
	      ADD	: out std_logic_vector(21 downto 0);
	      CEN	: out std_logic ;
	      WEN	: out std_logic ;
	      OEN	: out std_logic
	     );
end component;

component configuring
	port( CLK33	: in std_logic;
	      NSTATUS	: in std_logic;
	      DA	: in std_logic_vector(7 downto 0);
	      RSTB   	: in std_logic;
	      CONF_DONE	: in std_logic;
	      CONF_ST	: in std_logic;
	      MODE_U	: in std_logic;
	      DATA0	: out std_logic;
	      DCLK	: out std_logic;
	      NCONFIG	: out std_logic;
	      CONF_ADD	: out std_logic_vector(21 downto 0);
	      C_OEN	: out std_logic;
	      CONF_END	: out std_logic;
	      C_ERR	: out std_logic;
	      CONF_ERR	: out std_logic 
	     );
end component;
---------------------------------------------------------------------------------------------------
signal INIT_ST     : std_logic ;
signal CHECK_ST    : std_logic ;
signal READ_ST     : std_logic ;
signal VERI_ST     : std_logic ;
signal EN_FLASH    : std_logic ;
signal EN_APEX     : std_logic ;
signal EN_LAST     : std_logic ;
signal EN_VERIFY   : std_logic ;
signal VERI_ACK    : std_logic ;
signal CNT3V_C     : std_logic ;
signal COUNT       : std_logic_vector(2 downto 0) ;
signal DATA_OUT    : std_logic_vector(7 downto 0) ;
signal INIT_EN     : std_logic ;
signal MODE_U	   : std_logic ;
signal STB_UP      : std_logic ;
signal CMP         : std_logic ;
signal CONF_ADD    : std_logic_vector(21 downto 0) ;
signal CONF_ST     : std_logic ;
signal CONF_END    : std_logic ;
signal CONF_ERROR  : std_logic ;
signal temp_OEN    : std_logic ;
signal DA_O        : std_logic_vector(7 downto 0) ;
signal RD_C        : std_logic_vector(7 downto 0) ;
signal C_OEN       : std_logic ;
signal C_ERR       : std_logic ;
signal RD_P	   : std_logic ;
signal V_CMP	   : std_logic ;
signal V_CMP_L	   : std_logic ;
signal VERI_ERR    : std_logic ;
signal VERI_DA     : std_logic ;

begin
---------------------------------------------------------------------------------------------------
M0:pcif	port map( DATA_MODE => DATA_MODE,
	          DATA_PC   => DATA_PC,
	          STB	    => STB,
	          CLK33	    => CLK33,
	          RSTB	    => RSTB,
	          INIT_ST   => INIT_ST,
		  VERI_ST   => VERI_ST,
		  VERI_ACK  => VERI_ACK,
 	          EN_FLASH  => EN_FLASH,
	          EN_APEX   => EN_APEX,
	          EN_LAST   => EN_LAST,
		  EN_VERIFY => EN_VERIFY,
  	          DATA_OUT  => DATA_OUT,
	          INIT_EN   => INIT_EN,
		  MODE_U    => MODE_U,
		  STB_UP    => STB_UP,
		  CNT3V_C   => CNT3V_C,
		  COUNT     => COUNT,
	          ACK	    => ACK
	         );

M1:state port map( CLK33     => CLK33,
	   	   RSTB	     => RSTB,
              	   STS	     => STS,
	      	   CMP	     => CMP,
	      	   DATA_OUT  => DATA_OUT,
	      	   C_OEN     => C_OEN,
	      	   EN_FLASH  => EN_FLASH,
	      	   EN_APEX   => EN_APEX,
	      	   EN_LAST   => EN_LAST,
		   EN_VERIFY => EN_VERIFY,
	      	   CONF_END  => CONF_END,
	      	   CONF_ADD  => CONF_ADD,
	      	   INIT_EN   => INIT_EN,
	      	   C_ERR     => C_ERR,
	      	   VERI_ERR  => VERI_ERR,
		   CNT3V_C   => CNT3V_C,
		   CHECK_ST  => CHECK_ST,
		   READ_ST   => READ_ST,
	      	   INIT_ST   => INIT_ST,
	      	   CONF_ST   => CONF_ST,
		   VERI_ST   => VERI_ST,
	      	   FLASH_RUN => FLASH_RUN,
	      	   ERASE_RUN => ERASE_RUN,
	      	   RD_P	     => RD_P,
		   VERI_ACK  => VERI_ACK,
	      	   DA	     => DA_O,
	      	   ADD	     => ADD,
	      	   CEN	     => CEN,
	      	   WEN	     => WEN,
	      	   OEN	     => temp_OEN
		);

M2:configuring port map( CLK33	   => CLK33,
	      		 NSTATUS   => NSTATUS,
	      		 DA        => DA,
	      		 RSTB      => RSTB,
	      		 CONF_DONE => CONF_DONE,
	      		 CONF_ST   => CONF_ST,
	      		 MODE_U    => MODE_U,
	      		 DATA0	   => DATA0,
	      		 DCLK	   => DCLK,
	      		 NCONFIG   => NCONFIG,
	      		 CONF_ADD  => CONF_ADD,
	      		 C_OEN	   => C_OEN,
	      		 CONF_END  => CONF_END,
	      		 C_ERR	   => C_ERR,
	      		 CONF_ERR  => CONF_ERROR
			);

-- I/O control ------------------------------------------------------------------------------------
	OEN <= temp_OEN ;
	DA <= DA_O when temp_OEN='1' else (others=>'Z') ;

-- SPECIAL ADDRESS DATA COMPARE & VERIFY FLASH MEMORY CONTENT & VERIFY CHECK ----------------------
	process (CLK33,RSTB) begin
		if (RSTB='0') then
			RD_C <= (others => '0') ;
		elsif (CLK33' event and CLK33='1') then
			if (RD_P='1' and CHECK_ST='1') then
				RD_C <= DA ;
			end if ;
		end if ;
	end process ;

	CMP <= '1' when RD_C = "10100101" else '0' ;

	V_CMP <= '0' when (DA = DATA_OUT) else '1' ;
	V_CMP_L <= '0' when (DA = "10100101") else '1' ;

	process (CLK33,RSTB) begin
		if (RSTB='0') then
			VERI_ERR <= '0' ;
		elsif (CLK33' event and CLK33='1') then
			if (MODE_U='1') then
				VERI_ERR <= '0' ;
			elsif (RD_P='1' and READ_ST='1') then
				if (EN_LAST='1') then
					VERI_ERR <= V_CMP_L ;
				else
					VERI_ERR <= V_CMP ;
				end if ;
			end if ;
		end if ;
	end process ;

	process (CLK33,RSTB) begin
		if (RSTB='0')then
			VERI_DA <= '0' ;
		elsif (CLK33'event and CLK33='1')then
			if (VERI_ST='0') then
				VERI_DA <= '0' ;
			elsif (VERI_ST='1' and STB_UP='1') then
				case COUNT is
					when "000" => VERI_DA <= DA(0) ;
					when "001" => VERI_DA <= DA(1) ;
					when "010" => VERI_DA <= DA(2) ;
					when "011" => VERI_DA <= DA(3) ;
					when "100" => VERI_DA <= DA(4) ;
					when "101" => VERI_DA <= DA(5) ;
					when "110" => VERI_DA <= DA(6) ;
					when "111" => VERI_DA <= DA(7) ;
					when others => VERI_DA <= '0' ;
				end case ;
			end if ;
		end if ;
	end process ;

-- ETC --------------------------------------------------------------------------------------------
	CONF_STATUS <= VERI_ERR or CONF_ERROR or VERI_DA ;
	CONF_ERR <= CONF_ERROR ;
	CONF_RUN <= not(CONF_DONE) when CONF_ST='1' else '0';
	FLASH_ERR <= VERI_ERR ; 

---------------------------------------------------------------------------------------------------
end rtl;