xllp_resumephase2a.lst
来自「pxa270为硬件平台的wince操作系统XLLP驱动源码」· LST 代码 · 共 918 行 · 第 1/5 页
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918 行
242 00000000
243 00000000 ;
244 00000000 ; Optimal values for DTC settings for various MemClk settings (MDCNFG)
245 00000000 ;
246 00000000 IF :DEF: xlli_SDRAM_WIDTH_16_BIT
331 00000000 ELSE ; ELSE not 16 bit SDRAM width
332 00000000
333 00000000 xlli_DTC_13 EQU (0x00000000) ; 13 MHz setting
334 00000000 xlli_DTC_19 EQU (0x00000000) ; 19 MHz setting
335 00000000 xlli_DTC_26 EQU (0x00000000) ; 26 MHz setting
336 00000000 xlli_DTC_32 EQU (0x00000000) ; 32 MHz setting
337 00000000 xlli_DTC_39 EQU (0x00000000) ; 39 MHz setting
338 00000000 xlli_DTC_45 EQU (0x00000000) ; 45 MHz setting
339 00000000 xlli_DTC_52 EQU (0x00000000) ; 52 MHz setting
340 00000000 xlli_DTC_58 EQU (0x01000100) ; 58 MHz setting
341 00000000 xlli_DTC_65 EQU (0x01000100) ; 65 MHz setting
342 00000000 xlli_DTC_68 EQU (0x01000100) ; 68 MHz setting
343 00000000 xlli_DTC_71 EQU (0x01000100) ; 71 MHz setting
344 00000000 xlli_DTC_74 EQU (0x01000100) ; 74 MHz setting
345 00000000 xlli_DTC_78 EQU (0x01000100) ; 78 MHz setting
346 00000000 xlli_DTC_81 EQU (0x01000100) ; 81 MHz setting
347 00000000 xlli_DTC_84 EQU (0x01000100) ; 84 MHz setting
348 00000000 xlli_DTC_87 EQU (0x01000100) ; 87 MHz setting
349 00000000 xlli_DTC_91 EQU (0x02000200) ; 91 MHz setting
350 00000000 xlli_DTC_94 EQU (0x02000200) ; 94 MHz setting
351 00000000 xlli_DTC_97 EQU (0x02000200) ; 97 MHz setting
352 00000000 xlli_DTC_100 EQU (0x02000200) ; 100 MHz setting
353 00000000 xlli_DTC_104 EQU (0x02000200) ; 104 MHz setting
354 00000000 xlli_DTC_110 EQU (0x01000100) ; 110 MHz setting - SDCLK Halved
355 00000000 xlli_DTC_117 EQU (0x01000100) ; 117 MHz setting - SDCLK Halved
356 00000000 xlli_DTC_124 EQU (0x01000100) ; 124 MHz setting - SDCLK Halved
357 00000000 xlli_DTC_130 EQU (0x01000100) ; 130 MHz setting - SDCLK Halved
358 00000000 xlli_DTC_136 EQU (0x01000100) ; 136 MHz setting - SDCLK Halved
359 00000000 xlli_DTC_143 EQU (0x01000100) ; 143 MHz setting - SDCLK Halved
360 00000000 xlli_DTC_149 EQU (0x01000100) ; 149 MHz setting - SDCLK Halved
361 00000000 xlli_DTC_156 EQU (0x01000100) ; 156 MHz setting - SDCLK Halved
362 00000000 xlli_DTC_162 EQU (0x01000100) ; 162 MHz setting - SDCLK Halved
363 00000000 xlli_DTC_169 EQU (0x01000100) ; 169 MHz setting - SDCLK Halved
364 00000000 xlli_DTC_175 EQU (0x01000100) ; 175 MHz setting - SDCLK Halved
365 00000000 xlli_DTC_182 EQU (0x02000200) ; 182 MHz setting - SDCLK Halved - Close to edge, so bump up
366 00000000 xlli_DTC_188 EQU (0x02000200) ; 188 MHz setting - SDCLK Halved - Close to edge, so bump up
367 00000000 xlli_DTC_195 EQU (0x02000200) ; 195 MHz setting - SDCLK Halved - Close to edge, so bump up
368 00000000 xlli_DTC_201 EQU (0x02000200) ; 201 MHz setting - SDCLK Halved - Close to edge, so bump up
369 00000000 xlli_DTC_208 EQU (0x02000200) ; 208 MHz setting - SDCLK Halved - Close to edge, so bump up
370 00000000
371 00000000 ;
372 00000000 ; Optimal values for DRI settings for various MemClk settings (MDREFR)
373 00000000 ;
374 00000000 xlli_DRI_13 EQU (0x002) ; 13 MHz setting
375 00000000 xlli_DRI_19 EQU (0x003)
376 00000000 xlli_DRI_26 EQU (0x005) ; 26 MHz setting
377 00000000 xlli_DRI_32 EQU (0x006)
378 00000000 xlli_DRI_39 EQU (0x008) ; 39 MHz setting
379 00000000 xlli_DRI_45 EQU (0x00A)
380 00000000 xlli_DRI_52 EQU (0x00B) ; 52 MHz setting
381 00000000 xlli_DRI_58 EQU (0x00D)
382 00000000 xlli_DRI_65 EQU (0x00E) ; 65 MHz setting
383 00000000 xlli_DRI_68 EQU (0x00F)
384 00000000 xlli_DRI_71 EQU (0x010) ; 71 MHz setting
385 00000000 xlli_DRI_74 EQU (0x011)
386 00000000 xlli_DRI_78 EQU (0x012) ; 78 MHz setting
387 00000000 xlli_DRI_81 EQU (0x012)
388 00000000 xlli_DRI_84 EQU (0x013) ; 84 MHz setting
389 00000000 xlli_DRI_87 EQU (0x014)
390 00000000 xlli_DRI_91 EQU (0x015) ; 91 MHz setting
391 00000000 xlli_DRI_94 EQU (0x016) ; 94 MHz setting
392 00000000 xlli_DRI_97 EQU (0x016) ; 97 MHz setting
393 00000000 xlli_DRI_100 EQU (0x017) ; 100 MHz setting
394 00000000 xlli_DRI_104 EQU (0x018) ; 104 MHz setting
395 00000000 xlli_DRI_110 EQU (0x01A)
396 00000000 xlli_DRI_117 EQU (0x01B) ; 117 MHz setting
397 00000000 xlli_DRI_124 EQU (0x01D)
398 00000000 xlli_DRI_130 EQU (0x01E) ; 130 MHz setting
399 00000000 xlli_DRI_136 EQU (0x020)
400 00000000 xlli_DRI_143 EQU (0x021)
401 00000000 xlli_DRI_149 EQU (0x023)
402 00000000 xlli_DRI_156 EQU (0x025)
403 00000000 xlli_DRI_162 EQU (0x026)
404 00000000 xlli_DRI_169 EQU (0x028) ; 169 MHz setting
405 00000000 xlli_DRI_175 EQU (0x029)
406 00000000 xlli_DRI_182 EQU (0x02B)
407 00000000 xlli_DRI_188 EQU (0x02D)
408 00000000 xlli_DRI_195 EQU (0x02E)
409 00000000 xlli_DRI_201 EQU (0x030)
410 00000000 xlli_DRI_208 EQU (0x031) ; 208 MHz setting
411 00000000
412 00000000 ENDIF ; xlli_SDRAM_WIDTH_16_BIT
413 00000000
414 00000000 ;
415 00000000 ; SDRAM Settings
416 00000000 ;
417 00000000 IF :DEF: xlli_SDRAM_WIDTH_16_BIT
419 00000000 ELSE
420 00000000 xlli_MDCNFG_value EQU (0x00000AC8) ; SDRAM Config Reg (Non-MCP Version)
421 00000000 ENDIF
422 00000000
423 00000000 xlli_MDMRS_value EQU (0x00000000) ; SDRAM Mode Reg Set Config Reg
424 00000000
425 00000000 ;
426 00000000 ; MEMORY PHYSICAL BASE ADDRESS(S)
427 00000000 ;
428 00000000
429 00000000 xlli_SRAM_PHYSICAL_BASE EQU (0X5C000000) ; Physical base address for SRAM
430 00000000 xlli_SDRAM_PHYSICAL_BASE EQU (0xA0000000) ; Physical base address for SDRAM
431 00000000
432 00000000 ;
433 00000000 ; CORE, SYSTEM BUS, MEMORY BUS Default frequency setting for Mainstone
434 00000000 ;
435 00000000 xlli_CCCR_value EQU (0x00000107) ; PXA27x (HW reset value to start)
436 00000000 ;
437 00000000 ; Clock Enable Register (CKEN) setting
438 00000000 ;
439 00000000 xlli_CKEN_value EQU (0x00400240) ; Data to be set into the clock enable register
440 00000000 ; Bit 6 enables FFUART
441 00000000 ; bit 9 enables OS timers
442 00000000 ; Bit 22 enables memory clock
443 00000000 ;
444 00000000 ; Address where system configuration data is stored
445 00000000 ;
446 00000000 xlli_SCR_data EQU 0x5C03FFFC ; Address of system config data
447 00000000
448 00000000 ;
449 00000000 ; Misc constants
450 00000000 ;
451 00000000 xlli_MemSize_1Mb EQU 0x00100000
452 00000000 IF :DEF: xlli_SDRAM_SIZE_32_MB
454 00000000 ENDIF
455 00000000 IF :DEF: xlli_SDRAM_SIZE_64_MB
456 00000000 xlli_p_PageTable EQU 0xA3FFC000 ; Base address for memory Page Table (Non-MCP version)
457 00000000 ENDIF
458 00000000 IF :DEF: xlli_SDRAM_SIZE_128_MB
460 00000000 ENDIF
461 00000000 xlli_s_PageTable EQU 0x00004000 ; Page Table size (4K words - 16 Kb)
462 00000000
463 00000000
464 00000000 xlli_FLASH_WRITE_CMD EQU 0x0060 ; Code for writing to flash
465 00000000 xlli_FLASH_WCONF_CMD EQU 0x0003 ; Code to confirm write to flash
466 00000000 xlli_FLASH_READ_CMD EQU 0x00FF ; Code to place flash in read mode
467 00000000 xlli_FLASH_READQUERY_CMD EQU 0x0098 ; Code to place flash in a 'query CFI' mode
468 00000000
469 00000000 ;
470 00000000 ; Note 1: For the current L3/L18 flash, it has a maximium frequency of 52MHz. In addition, the SXCNFG.LC value is based on t
he
471 00000000 ; SDClk presented to the flash, not the MEMClk as with most other Memory Controller settings, a bit odd, but so be it
.
472 00000000 ;
473 00000000 ; Note 2: We have just optimized these values for 52MHz SDClk to the Flash part. The OEM could optimize this for other SDClk
values,
474 00000000 ; but as there are so many, and the predominant Intel supported frequencies put the flash part into 52MHz operation,
it
475 00000000 ; made more sense to focus on the code, as each OEM will decide how best to run/optimize their platform.
476 00000000 ;
477 00000000 ; Explaination of RCR value:
478 00000000 ;
479 00000000 ; Read Mode = 0x0 = Sync. Mode
480 00000000 ; Latency Count = 0x5
481 00000000 ; Wait Polarity = 0x0 = Wait active low
482 00000000 ; Data Hold = 0x0 = Hold for 1 clock
483 00000000 ; Wait Delay = 0x1 = Wait de-asserted 1 dcycle before valid data
484 00000000 ; Burst Sequence = 0x1 = Linear
485 00000000 ; Clock Edge = 0x1 = Rising
486 00000000 ; Burst Wrap = 0x0 = wrap
487 00000000 ; Burst length = 0x3 = 16 word burst
488 00000000 ;
489 00000000 ; Note on Burst Length: Spacial locality suggests that having a burst of 16 will give better results than that of 8, ho
wever,
490 00000000 ; be aware that 8 words is a cache line, so it may be more beneficial to revert to a burst length of 8 words per
491 00000000 ; burst as opposed to 16 words per burst
492 00000000 ;
493 00000000 xlli_FLASH_RCR16_value EQU 0x25C3<<1 ; Value to set flash into sync mode - optimal RC.LC value for 52MHz flash is 5
494 00000000 xlli_FLASH_RCR32_value EQU 0x25C3<<2 ; Value to set flash into sync mode - optimal RC.LC value for 52MHz flash is 5
495 00000000
496 00000000 ;
497 00000000 ; Value below is simply to align with the settings put in for the flash RCR value
498 00000000 ;
499 00000000 xlli_SXCNFG_sync_value EQU 0x7011 ; SXCNFG value for sync flash operation - optimal SXCNFG.LC value for 52MHz fl
ash is 4
500 00000000
501 00000000 ;
502 00000000 ; Values to put the flash back into Asynchronous mode
503 00000000 ;
504 00000000 xlli_FLASH_ASYNC_RCR16_value ⌨️ 快捷键说明
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