xllp_resumephase2a.lst
来自「pxa270为硬件平台的wince操作系统XLLP驱动源码」· LST 代码 · 共 918 行 · 第 1/5 页
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336 00000000
337 00000000 xlli_OSCC_OOK EQU (0x01) ; Oscillator OK bit
338 00000000 xlli_OSCC_OON EQU (0x02) ; Timekeeping (32.768KHz) Osc bit
339 00000000 xlli_OSCC_TOUT_EN EQU (0x04) ; Timekeeping Output enable
340 00000000 xlli_OSCC_PIO_EN EQU (0x08) ; Processor Oscillator Output Enable
341 00000000 xlli_OSCC_CRI EQU (0x10) ; Processor Oscillator Output Enable
342 00000000
343 00000000 ;
344 00000000 ; Coprocessor 15 data bits
345 00000000 ;
346 00000000
347 00000000 xlli_control_icache EQU (0x1000) ; bit 12 - i-cache bit
348 00000000 xlli_control_btb EQU (0x0800) ; bit 11 - btb bit
349 00000000 xlli_control_r EQU (0x0200) ; Bit 9
350 00000000 xlli_control_s EQU (0x0100) ; Bit 8
351 00000000 xlli_control_dcache EQU (0x0004) ; Bit 2 - d-cache bit
352 00000000 xlli_control_mmu EQU (0x0001) ; Bit 0 - MMU bit
353 00000000
354 00000000
355 00000000 ;
356 00000000 ; CP 15 related settings
357 00000000 ;
358 00000000
359 00000000 xlli_PID EQU (0x00)
360 00000000 xlli_DACR EQU (0x01)
361 00000000 xlli_CONTROL_DCACHE EQU (0x04)
362 00000000 xlli_CONTROL_MINIDATA_01 EQU (0x10)
363 00000000 xlli_CONTROL_BTB EQU (0x800) ; Brach Target Buffer bit
364 00000000
365 00000000 ;
366 00000000 ; register bit masks - RCSR
367 00000000 ;
368 00000000 xlli_RCSR_HWR EQU (0x01)
369 00000000 xlli_RCSR_WDR EQU (0x02)
370 00000000 xlli_RCSR_SMR EQU (0x04)
371 00000000 xlli_RCSR_GPR EQU (0x08)
372 00000000 xlli_RCSR_ALL EQU (0xF)
373 00000000
374 00000000
375 00000000 ;
376 00000000 ; CPSR Processor constants
377 00000000
378 00000000 xlli_CPSR_Mode_MASK EQU (0x0000001F)
379 00000000 xlli_CPSR_Mode_USR EQU (0x10)
380 00000000 xlli_CPSR_Mode_FIQ EQU (0x11)
381 00000000 xlli_CPSR_Mode_IRQ EQU (0x12)
382 00000000 xlli_CPSR_Mode_SVC EQU (0x13)
383 00000000 xlli_CPSR_Mode_ABT EQU (0x17)
384 00000000 xlli_CPSR_Mode_UND EQU (0x1B)
385 00000000 xlli_CPSR_Mode_SYS EQU (0x1F)
386 00000000
387 00000000 xlli_CPSR_I_Bit EQU (0x80)
388 00000000 xlli_CPSR_F_Bit EQU (0x40)
389 00000000
390 00000000
391 00000000 xlli_PWRMODE_SLEEP EQU (0x00000003) ; Value for cp14: Reg7 to induce sleep.
392 00000000 ; Bit settings
393 00000000 ;
394 00000000 xlli_BIT_0 EQU 0x00000001
395 00000000 xlli_BIT_1 EQU 0x00000002
396 00000000 xlli_BIT_2 EQU 0x00000004
397 00000000 xlli_BIT_3 EQU 0x00000008
398 00000000 xlli_BIT_4 EQU 0x00000010
399 00000000 xlli_BIT_5 EQU 0x00000020
400 00000000 xlli_BIT_6 EQU 0x00000040
401 00000000 xlli_BIT_7 EQU 0x00000080
402 00000000 xlli_BIT_8 EQU 0x00000100
403 00000000 xlli_BIT_9 EQU 0x00000200
404 00000000 xlli_BIT_10 EQU 0x00000400
405 00000000 xlli_BIT_11 EQU 0x00000800
406 00000000 xlli_BIT_12 EQU 0x00001000
407 00000000 xlli_BIT_13 EQU 0x00002000
408 00000000 xlli_BIT_14 EQU 0x00004000
409 00000000 xlli_BIT_15 EQU 0x00008000
410 00000000 xlli_BIT_16 EQU 0x00010000
411 00000000 xlli_BIT_17 EQU 0x00020000
412 00000000 xlli_BIT_18 EQU 0x00040000
413 00000000 xlli_BIT_19 EQU 0x00080000
414 00000000 xlli_BIT_20 EQU 0x00100000
415 00000000 xlli_BIT_21 EQU 0x00200000
416 00000000 xlli_BIT_22 EQU 0x00400000
417 00000000 xlli_BIT_23 EQU 0x00800000
418 00000000 xlli_BIT_24 EQU 0x01000000
419 00000000 xlli_BIT_25 EQU 0x02000000
420 00000000 xlli_BIT_26 EQU 0x04000000
421 00000000 xlli_BIT_27 EQU 0x08000000
422 00000000 xlli_BIT_28 EQU 0x10000000
423 00000000 xlli_BIT_29 EQU 0x20000000
424 00000000 xlli_BIT_30 EQU 0x40000000
425 00000000 xlli_BIT_31 EQU 0x80000000
426 00000000 END
33 00000000 INCLUDE xllp_ResumePhase2_Data.inc
1 00000000 IF !:DEF: _xllp_ResumePhase2_Data_included
2 00000000 xllp_ResumePhase2_Data_included EQU 1
3 00000000 ;******************************************************************************
4 00000000 ;
5 00000000 ; COPYRIGHT (C) 2005 Intel Corporation.
6 00000000 ;
7 00000000 ; This software as well as the software described in it is furnished under
8 00000000 ; license and may only be used or copied in accordance with the terms of the
9 00000000 ; license. The information in this file is furnished for informational use
10 00000000 ; only, is subject to change without notice, and should not be construed as
11 00000000 ; a commitment by Intel Corporation. Intel Corporation assumes no
12 00000000 ; responsibility or liability for any errors or inaccuracies that may appear
13 00000000 ; in this document or any software that may be provided in association with
14 00000000 ; this document.
15 00000000 ;
16 00000000 ; Except as permitted by such license, no part of this document may be
17 00000000 ; reproduced, stored in a retrieval system, or transmitted in any form or by
18 00000000 ; any means without the express written consent of Intel Corporation.
19 00000000 ;
20 00000000 ;******************************************************************************
21 00000000 RESUMEPHASE2_WORD_SIZE EQU 4
22 00000000 RESUMEPHASE2_DATA_START EQU 0
23 00000000
24 00000000 RESUMEPHASE2_CHECKSUM_OFFSET EQU (RESUMEPHASE2_DATA_START)
25 00000000 RESUMEPHASE2_WORDCOUNT_OFFSET EQU (RESUMEPHASE2_CHECKSUM_OFFSET + RESUMEPHASE2_WORD_SIZE)
26 00000000 RESUMEPHASE2_SP_OFFSET EQU (RESUMEPHASE2_WORDCOUNT_OFFSET + RESUMEPHASE2_WORD_SIZE)
27 00000000 RESUMEPHASE2_CPSR_OFFSET EQU (RESUMEPHASE2_SP_OFFSET + RESUMEPHASE2_WORD_SIZE)
28 00000000 RESUMEPHASE2_CPAR_OFFSET EQU (RESUMEPHASE2_CPSR_OFFSET + RESUMEPHASE2_WORD_SIZE)
29 00000000 RESUMEPHASE2_RESUMEPHASE3_PC_OFFSET EQU (RESUMEPHASE2_CPAR_OFFSET + RESUMEPHASE2_WORD_SIZE)
30 00000000 ; Coprocessor registers
31 00000000 RESUMEPHASE2_CP15_ACR_MMU_OFFSET EQU (RESUMEPHASE2_RESUMEPHASE3_PC_OFFSET + RESUMEPHASE2_WORD_SIZE)
32 00000000 RESUMEPHASE2_CP15_AUXCR_MMU_OFFSET EQU (RESUMEPHASE2_CP15_ACR_MMU_OFFSET + RESUMEPHASE2_WORD_SIZE)
33 00000000 RESUMEPHASE2_CP15_TTBR_MMU_OFFSET EQU (RESUMEPHASE2_CP15_AUXCR_MMU_OFFSET + RESUMEPHASE2_WORD_SIZE)
34 00000000 RESUMEPHASE2_CP15_DACR_MMU_OFFSET EQU (RESUMEPHASE2_CP15_TTBR_MMU_OFFSET + RESUMEPHASE2_WORD_SIZE)
35 00000000 RESUMEPHASE2_CP15_PID_MMU_OFFSET EQU (RESUMEPHASE2_CP15_DACR_MMU_OFFSET + RESUMEPHASE2_WORD_SIZE)
36 00000000
37 00000000 RESUMEPHASE2_DATA_END EQU (RESUMEPHASE2_CP15_PID_MMU_OFFSET + RESUMEPHASE2_WORD_SIZE)
38 00000000 RESUMEPHASE2_DATA_SIZE EQU (RESUMEPHASE2_DATA_END - RESUMEPHASE2_DATA_START)
39 00000000 RESUMEPHASE2_DATA_WORDS EQU (RESUMEPHASE2_DATA_SIZE / RESUMEPHASE2_WORD_SIZE)
40 00000000
41 00000000 ENDIF
42 00000000 END
34 00000000 INCLUDE xllp_ARM_macros.inc
1 00000000 IF !:DEF: _xllp_arm_macros_included
2 00000000 xllp_arm_macros_included EQU 1
3 00000000 ;******************************************************************************
4 00000000 ;
5 00000000 ; COPYRIGHT (C) 2005 Intel Corporation.
6 00000000 ;
7 00000000 ; This software as well as the software described in it is furnished under
8 00000000 ; license and may only be used or copied in accordance with the terms of the
9 00000000 ; license. The information in this file is furnished for informational use
10 00000000 ; only, is subject to change without notice, and should not be construed as
11 00000000 ; a commitment by Intel Corporation. Intel Corporation assumes no
12 00000000 ; responsibility or liability for any errors or inaccuracies that may appear
13 00000000 ; in this document or any software that may be provided in association with
14 00000000 ; this document.
15 00000000 ;
16 00000000 ; Except as permitted by such license, no part of this document may be
17 00000000 ; reproduced, stored in a retrieval system, or transmitted in any form or by
18 00000000 ; any means without the express written consent of Intel Corporation.
19 00000000 ;
20 00000000 ;******************************************************************************
21 00000000
22 00000000 MACRO
23 00000000 RETURN
24 00000000 IF :DEF: Interworking
25 00000000 IF Interworking :LOR: Thumbing
26 00000000 bx lr
27 00000000 ELSE
28 00000000 mov pc, lr ; return
29 00000000 ENDIF ; ELSE of IF Interworking :LOR: Thumbing
30 00000000 ELSE ; IF :DEF: Interworking
31 00000000 mov pc, lr ; return
32 00000000 ENDIF ; ELSE OF IF :DEF: Interworking
33 00000000
34 00000000 MEND
35 00000000
36 00000000 ;;------------------------------------------------------------------------------
37 00000000 ENDIF
38 00000000 END
35 00000000 IF :DEF: BSP_MAINSTONE
36 00000000 INCLUDE xlli_mainstone_defs.inc ; needed for hex led display
1 00000000 ;*********************************************************************************
2 00000000 ;
3 00000000 ; COPYRIGHT (c) 2002 - 2004 Intel Corporation
4 00000000 ;
5 00000000 ; The information in this file is furnished for informational use only,
6 00000000 ; is subject to change without notice, and should not be construed as
7 00000000 ; a commitment by Intel Corporation. Intel Corporation assumes no
8 00000000 ; responsibility or liability for any errors or inaccuracies that may appear
9 00000000 ; in this document or any software that may be provided in association with
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