xllp_resumephase2a.lst
来自「pxa270为硬件平台的wince操作系统XLLP驱动源码」· LST 代码 · 共 918 行 · 第 1/5 页
LST
918 行
10 00000000 ; this document.
11 00000000 ;
12 00000000 ;*********************************************************************************
13 00000000 ;
14 00000000 ; FILENAME: xlli_Mainstone_defs.inc (Platform specific addresses and
15 00000000 ; defalut values for Mainstone II platform bring up)
16 00000000 ; NOTE: - This file has a def to configure xlli for MCP and non-MCP processors
17 00000000 ;
18 00000000 ; LAST MODIFIED: 4-Aug-2004
19 00000000 ;
20 00000000 ;******************************************************************************
21 00000000 ;
22 00000000 ;
23 00000000 ; Include file for Mainstone II specific Cross Platform Low Level Initialization (XLLI)
24 00000000 ;
25 00000000 ;
26 00000000 ;******************************************************************************
27 00000000
28 00000000
29 00000000 ;
30 00000000 ; CONFIGURATION OPTIONS
31 00000000 ; Note: As there are multiple configuration options and a limited number of switches, it is
32 00000000 ; necessary to make some things compile time specific. WinCE does not use the SDRAM, FLASH
33 00000000 ; or C0 flags, as they are passed via the build environment, but it does use the UART
34 00000000 ; definition
35 00000000 ;
36 00000000
37 00000000 ;xlli_SDRAM_SIZE_32_MB EQU 0 ; Uncomment for 64 Mb of SDRAM
38 00000000 ;xlli_SDRAM_WIDTH_16_BIT EQU 0 ; Uncomment for 16-bit SDRAM bus
39 00000000 ;xlli_FLASH_WIDTH_16_BIT EQU 0 ; Uncomment for 16-bit FLASH bus
40 00000000 ;xlli_C0_BULVERDE EQU 0 ; Uncomment for PXA27x step C0
41 00000000
42 00000000 ;
43 00000000 ; Uncomment out the UART you want for your platform (ffuart, stuart or btuart), but
44 00000000 ; only choose ONE!
45 00000000 ;
46 00000000 ;xlli_Target_UART EQU (xlli_perif_base + xlli_ffuart_offset) ; Uncomment for the ffuart
47 00000000 ;xlli_Target_UART EQU (xlli_perif_base + xlli_stuart_offset) ; Uncomment for the stuart
48 00000000 xlli_Target_UART EQU (xlli_perif_base + xlli_btuart_offset) ; Uncomment for the btuart
49 00000000
50 00000000
51 00000000 ;
52 00000000 ; PLATFORM REGISTERS base address and register offsets from the base address
53 00000000 ;
54 00000000 xlli_PLATFORM_REGISTERS EQU 0x08000000
55 00000000
56 00000000 xlli_PLATFORM_HEXLED_DATA_offset EQU 0x10 ; Hex LED Data Register
57 00000000 xlli_PLATFORM_LED_CONTROL_offset EQU 0x40 ; LED Control Register
58 00000000 xlli_PLATFORM_SWITCH_offset EQU 0x60 ; General Purpose Switch Register
59 00000000 xlli_PLATFORM_MISC_WRITE1_offset EQU 0x80 ; Misc Write Register 1
60 00000000 xlli_PLATFORM_MISC_WRITE2_offset EQU 0x84 ; Misc Write Register 2
61 00000000 xlli_PLATFORM_MISC_READ1_offset EQU 0x90 ; Misc Read Register 1
62 00000000 xlli_PLATFORM_INTERR_ME_offset EQU 0xC0 ; Platform Interrupt Mask/Enable Register 1
63 00000000 xlli_PLATFORM_INTERR_SC_offset EQU 0xD0 ; Platform Interrupt Set/Clear Register 1
64 00000000 xlli_PLATFORM_PCMCIA0_SC_offset EQU 0xE0 ; PCMCIA Socket 0 Status/Control Register
65 00000000 xlli_PLATFORM_PCMCIA1_SC_offset EQU 0xE4 ; PCMCIA Socket 1 Status/Control Register
66 00000000
67 00000000 ;
68 00000000 ; Platform specific bits
69 00000000 ;
70 00000000 xlli_SYS_RESET EQU 0x01 ; System reset bit
71 00000000
72 00000000 ;
73 00000000 ; platform GPIO pin settings (PXA27x/Mainstone)
74 00000000 ;
75 00000000 xlli_GPSR0_value EQU (0x00008004) ; Set registers
76 00000000 xlli_GPSR1_value EQU (0x00020080)
77 00000000 xlli_GPSR2_value EQU (0x16C14000)
78 00000000 xlli_GPSR3_value EQU (0x0003E000)
79 00000000
80 00000000 xlli_GPCR0_value EQU (0x0) ; Clear registers
81 00000000 xlli_GPCR1_value EQU (0x00000380) ; FFUART related
82 00000000 xlli_GPCR2_value EQU (0x0)
83 00000000 xlli_GPCR3_value EQU (0x0)
84 00000000
85 00000000 xlli_GRER0_value EQU (0x0) ; Rising Edge Detect
86 00000000 xlli_GRER1_value EQU (0x0)
87 00000000 xlli_GRER2_value EQU (0x0)
88 00000000 xlli_GRER3_value EQU (0x0)
89 00000000
90 00000000 xlli_GFER0_value EQU (0x0) ; Falling Edge Detect
91 00000000 xlli_GFER1_value EQU (0x0)
92 00000000 xlli_GFER2_value EQU (0x0)
93 00000000 xlli_GFER3_value EQU (0x0)
94 00000000
95 00000000 xlli_GPLR0_value EQU (0x0) ; Pin Level Registers
96 00000000 xlli_GPLR1_value EQU (0x0)
97 00000000 xlli_GPLR2_value EQU (0x0)
98 00000000 xlli_GPLR3_value EQU (0x0)
99 00000000
100 00000000 xlli_GEDR0_value EQU (0x0) ; Edge Detect Status
101 00000000 xlli_GEDR1_value EQU (0x0)
102 00000000 xlli_GEDR2_value EQU (0x0)
103 00000000 xlli_GEDR3_value EQU (0x0)
104 00000000
105 00000000 IF :DEF: POST_BUILD
112 00000000 ELSE
113 00000000
114 00000000 xlli_GPDR0_value EQU (0xCFE3BDE4) ; Direction Registers
115 00000000 xlli_GPDR1_value EQU (0x003FAB81)
116 00000000 xlli_GPDR2_value EQU (0x1EC3FC00)
117 00000000 xlli_GPDR3_value EQU (0x018FFE8F)
118 00000000
119 00000000 ENDIF
120 00000000
121 00000000 xlli_GAFR0_L_value EQU (0x84400000) ; Alternate function registers
122 00000000 xlli_GAFR0_U_value EQU (0xA5000510)
123 00000000 xlli_GAFR1_L_value EQU (0x000A9558)
124 00000000 xlli_GAFR1_U_value EQU (0x0005A1AA)
125 00000000 xlli_GAFR2_L_value EQU (0x60000000)
126 00000000 xlli_GAFR2_U_value EQU (0x00000802)
127 00000000 xlli_GAFR3_L_value EQU (0x00000000)
128 00000000 xlli_GAFR3_U_value EQU (0x00000000)
129 00000000
130 00000000 ;
131 00000000 ; MEMORY CONTROLLER SETTINGS FOR MAINSTONE
132 00000000 ;
133 00000000
134 00000000 xlli_MDREFR_value EQU (0x0000001E)
135 00000000 IF :DEF: xlli_FLASH_WIDTH_16_BIT
137 00000000 ELSE
138 00000000 xlli_MSC0_DC_value EQU (0x7FF0B8F2) ; PXA27x Card Flash value (Non-MCP version)
139 00000000 ENDIF
140 00000000 xlli_MSC0_MS_value EQU (0x23F2B8F2) ; Mainstone Board Flash value
141 00000000 xlli_MSC1_value EQU (0x0000CCD1)
142 00000000 xlli_MSC2_value EQU (0x0000B884)
143 00000000 xlli_MECR_value EQU (0x00000001)
144 00000000 xlli_MCMEM0_value EQU (0x00014307)
145 00000000 xlli_MCMEM1_value EQU (0x00014307)
146 00000000 xlli_MCATT0_value EQU (0x0001C787)
147 00000000 xlli_MCATT1_value EQU (0x0001C787)
148 00000000 xlli_MCIO0_value EQU (0x0001430F)
149 00000000 xlli_MCIO1_value EQU (0x0001430F)
150 00000000 xlli_FLYCNFG_value EQU (0x00010001)
151 00000000 xlli_MDMRSLP_value EQU (0x0000C008)
152 00000000 xlli_SXCNFG_value EQU (0x40044004) ; Default value at boot up
153 00000000
154 00000000
155 00000000 ;
156 00000000 ; Optimal values for MSCO for various MemClk frequencies are listed below
157 00000000 ; These values are for L18 async flash
158 00000000 ;
159 00000000 IF :DEF: xlli_C0_BULVERDE
160 00000000
161 00000000 xlli_MSC0_13 EQU (0x11101110)
162 00000000 xlli_MSC0_19 EQU (0x11101110)
163 00000000 xlli_MSC0_26 EQU (0x11201120) ; 26 MHz setting
164 00000000 xlli_MSC0_32 EQU (0x11201120)
165 00000000 xlli_MSC0_39 EQU (0x11301130) ; 39 MHz setting
166 00000000 xlli_MSC0_45 EQU (0x11301130)
167 00000000 xlli_MSC0_52 EQU (0x11401140) ; 52 MHz setting
168 00000000 xlli_MSC0_58 EQU (0x11401140)
169 00000000 xlli_MSC0_65 EQU (0x11501150) ; 65 MHz setting
170 00000000 xlli_MSC0_68 EQU (0x11501150)
171 00000000 xlli_MSC0_71 EQU (0x11501150) ; 71.5 MHz setting
172 00000000 xlli_MSC0_74 EQU (0x11601160)
173 00000000 xlli_MSC0_78 EQU (0x12601260) ; 78 MHz setting
174 00000000 xlli_MSC0_81 EQU (0x12601260)
175 00000000 xlli_MSC0_84 EQU (0x12601260) ; 84.5 MHz setting
176 00000000 xlli_MSC0_87 EQU (0x12701270)
177 00000000 xlli_MSC0_91 EQU (0x12701270) ; 91 MHz setting
178 00000000 xlli_MSC0_94 EQU (0x12701270) ; 94.2 MHz setting
179 00000000 xlli_MSC0_97 EQU (0x12701270) ; 97.5 MHz setting
180 00000000 xlli_MSC0_100 EQU (0x12801280) ; 100.7 MHz setting
181 00000000 xlli_MSC0_104 EQU (0x12801280) ; 104 MHz setting
182 00000000 xlli_MSC0_110 EQU (0x12901290)
183 00000000 xlli_MSC0_117 EQU (0x13901390) ; 117 MHz setting
184 00000000 xlli_MSC0_124 EQU (0x13A013A0)
185 00000000 xlli_MSC0_130 EQU (0x13A013A0) ; 130 MHz setting
186 00000000 xlli_MSC0_136 EQU (0x13B013B0)
187 00000000 xlli_MSC0_143 EQU (0x13B013B0)
188 00000000 xlli_MSC0_149 EQU (0x13C013C0)
189 00000000 xlli_MSC0_156 EQU (0x14C014C0)
190 00000000 xlli_MSC0_162 EQU (0x14C014C0)
191 00000000 xlli_MSC0_169 EQU (0x14C014C0)
192 00000000 xlli_MSC0_175 EQU (0x14C014C0)
193 00000000 xlli_MSC0_182 EQU (0x14C014C0)
194 00000000 xlli_MSC0_188 EQU (0x14C014C0)
195 00000000 xlli_MSC0_195 EQU (0x15C015C0)
196 00000000 xlli_MSC0_201 EQU (0x15D015D0)
197 00000000 xlli_MSC0_208 EQU (0x15D015D0)
198 00000000
199 00000000 ELSE
241 00000000 ENDIF ; xlli_C0_BULVERDE
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