ad9851.tan.rpt

用VHDL语言编写的DDS正弦函数发生器

; Worst-case th                ; N/A       ; None                             ; -0.818 ns                                      ; MPF[0]                     ; AD9851:inst2|DATA_TEMP[34]                                                                            ; --         ; MCU_CLK  ; 0            ;
; Clock Setup: 'SYS_CLK'       ; 14.578 ns ; 50.00 MHz ( period = 20.000 ns ) ; 184.43 MHz ( period = 5.422 ns )               ; AD9851:inst2|STAT[1]       ; AD9851:inst2|DAT_OUT[0]                                                                               ; SYS_CLK    ; SYS_CLK  ; 0            ;
; Clock Setup: 'MCU_CLK'       ; N/A       ; None                             ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; AD9851:inst2|DATA_TEMP[24] ; AD9851:inst2|DATA_TEMP[32]                                                                            ; MCU_CLK    ; MCU_CLK  ; 0            ;
; Clock Hold: 'SYS_CLK'        ; -2.461 ns ; 50.00 MHz ( period = 20.000 ns ) ; N/A                                            ; JUDGE:JUDGE|TEMP[0]        ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 ; SYS_CLK    ; SYS_CLK  ; 16           ;
; Total number of failed paths ;           ;                                  ;                                                ;                            ;                                                                                                       ;            ;          ; 16           ;
+------------------------------+-----------+----------------------------------+------------------------------------------------+----------------------------+-------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+-----------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                  ;
+-------------------------------------------------------+--------------------+------+---------+-------------+
; Option                                                ; Setting            ; From ; To      ; Entity Name ;
+-------------------------------------------------------+--------------------+------+---------+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;         ;             ;
; Timing Models                                         ; Final              ;      ;         ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;         ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;         ;             ;
; Number of paths to report                             ; 200                ;      ;         ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;         ;             ;
; Use Fast Timing Models                                ; Off                ;      ;         ;             ;
; Report IO Paths Separately                            ; Off                ;      ;         ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;         ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;         ;             ;
; Cut off read during write signal paths                ; On                 ;      ;         ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;         ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;         ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;         ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;         ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;         ;             ;
; Enable Clock Latency                                  ; Off                ;      ;         ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;         ;             ;
; Clock Settings                                        ; Clock              ;      ; SYS_CLK ;             ;
+-------------------------------------------------------+--------------------+------+---------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; SYS_CLK         ; CLOCK              ; User Pin ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; MCU_CLK         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'SYS_CLK'                                                                                                                                                                                                                                                                                                                                                                             ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+