ad9851.tan.rpt
来自「用VHDL语言编写的DDS正弦函数发生器」· RPT 代码 · 共 237 行 · 第 1/5 页
RPT
237 行
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 14.578 ns ; 184.43 MHz ( period = 5.422 ns ) ; AD9851:inst2|STAT[1] ; AD9851:inst2|DAT_OUT[0] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.780 ns ; 5.202 ns ;
; 14.656 ns ; 187.13 MHz ( period = 5.344 ns ) ; AD9851:inst2|STAT[2] ; AD9851:inst2|DAT_OUT[0] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.780 ns ; 5.124 ns ;
; 14.738 ns ; 190.04 MHz ( period = 5.262 ns ) ; AD9851:inst2|STAT[1] ; AD9851:inst2|STAT[3] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.739 ns ; 5.001 ns ;
; 14.739 ns ; 190.08 MHz ( period = 5.261 ns ) ; AD9851:inst2|STAT[1] ; AD9851:inst2|STAT[2] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.739 ns ; 5.000 ns ;
; 14.833 ns ; 193.54 MHz ( period = 5.167 ns ) ; AD9851:inst2|STAT[3] ; AD9851:inst2|DAT_OUT[0] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.780 ns ; 4.947 ns ;
; 14.887 ns ; 195.58 MHz ( period = 5.113 ns ) ; AD9851:inst2|STAT[1] ; AD9851:inst2|STAT[1] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.739 ns ; 4.852 ns ;
; 14.887 ns ; 195.58 MHz ( period = 5.113 ns ) ; AD9851:inst2|STAT[1] ; AD9851:inst2|STAT[0] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.739 ns ; 4.852 ns ;
; 14.889 ns ; 195.66 MHz ( period = 5.111 ns ) ; AD9851:inst2|STAT[2] ; AD9851:inst2|DAT_OUT[1] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.736 ns ; 4.847 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg7 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[23] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg6 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[23] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg5 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[23] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg4 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[23] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg3 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[23] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg2 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[23] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg1 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[23] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[23] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg7 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[15] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg6 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[15] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg5 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[15] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg4 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[15] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg3 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[15] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg2 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[15] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg1 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[15] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[15] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg7 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[22] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg6 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[22] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg5 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[22] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg4 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[22] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg3 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[22] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg2 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[22] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg1 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[22] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[22] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg7 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg6 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg5 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg4 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg3 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg2 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg1 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg0 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[30] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg7 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[14] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg6 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[14] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg5 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[14] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg4 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[14] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg3 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[14] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
; 14.924 ns ; 197.01 MHz ( period = 5.076 ns ) ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|ram_block1a7~porta_address_reg2 ; FM:ROM|altsyncram:altsyncram_component|altsyncram_jm21:auto_generated|q_a[14] ; SYS_CLK ; SYS_CLK ; 20.000 ns ; 19.243 ns ; 4.319 ns ;
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