txmit_tb.v

使用Verilog语言编写

`timescale 1ns/100ps

module txmit_tb;

	reg clk;
	reg clk_in;
	reg rst;
	reg [7:0] data;
	reg we;
	reg baud_clk;

	wire sdo;
	wire EF;
	wire AE;
	wire AF;
	wire FF;
	wire [3:0] count;

	txmit UUT (
		.clk(clk), 
		.clk_in(clk_in), 
		.rst(rst), 
		.data(data), 
		.we(we), 
		.baud_clk(baud_clk), 
		.sdo(sdo), 
		.EF(EF), 
		.AE(AE), 
		.AF(AF), 
		.FF(FF), 
		.count(count)
	);

	initial begin
		clk = 0;
		clk_in = 0 ;
		forever #(100/33) clk = ~clk ;
		end
		
	initial begin	
		baud_clk = 0;
		forever #500 baud_clk = ~baud_clk ;
		end
		
	initial begin	
		rst = 0;
		#20 rst = 1 ;
		#100 rst = 0 ;
		end
		
	initial begin	
		data = 0;
		#500 forever #500 data = data + 1;
		end
		
	initial begin	
		we = 0;
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;			
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;			
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;			
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;	
				#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;			
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;			
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;			
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
				#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;			
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;			
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;			
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;			
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;			
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;			
		#1000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#5000 we = 1 ; #500 we = 0 ;
		#180000	we = 1 ; #500 we = 0 ;			
		end


endmodule